Samsung Electronics Co., Ltd.

Se-Jun Park

Sung-Min Hwang

Jang-Gn Yun

Joon-Sung Lim

Choong-Ho Lee

Sun Choi

Zhiliang Xia

Ahn-Sik Moon

Woo-Yong Chang

Suk-Kang Sung

Min-Jeong Moon

Hee-Soo Kang

Dong-Hoon Jang

Keon-Soo Kim

Ji-Young Kwahk

Jung-dal Choi

Soo-Hong Park

Sang-Woong Hwang

Yoon-woo Jun

Yeon-hee Jung

Jin-Guk Jeong

Jee-sun Yoon

Jin-hyun Shin

Yoon-Moon Park

Joo-yeon Cho

Do-Hyoung Kim

Ju-Yun Sung

Jong-Sun Pyo

Hee-Jeong Choo

Seung-Wook Choi

Hang-Sik Shin

Seung-Dong Yu

Jae-Woo Ko

A vertical memory device includes a channel, a dummy channel, a plurality of gate electrodes, and a support pattern. The channel extends in a first direction perpendicular to an upper surface of a substrate. The dummy channel extends from the upper surface of the substrate in the first direction. The plurality of gate electrodes are formed at a plurality of levels, respectively, spaced apart from each other in the first direction on the substrate. Each of the gate electrodes surrounds outer sidewalls of the channel and the dummy channel. The support pattern is between the upper surface of the substrate and a first gate electrode among the gate electrodes. The first gate electrode is at a lowermost one of the levels. The channel and the dummy channel contact each other between the upper surface of the substrate and the first gate electrode.

Vertical memory devices and methods of manufacturing the same

A semiconductor device includes a plurality of insulation patterns and a plurality of gates alternately and repeatedly stacked on a substrate, a channel pattern extending through the gates in a first direction substantially perpendicular to a top surface of the substrate, a semiconductor pattern between the channel pattern and the substrate, and a conductive pattern between the channel pattern and the semiconductor pattern. The conductive pattern electrically connects the channel pattern to the semiconductor pattern. The conductive pattern contacts a bottom edge of the channel pattern and an upper surface of the semiconductor pattern.

Semiconductor devices including a conductive pattern contacting a channel pattern and methods of manufacturing the same

A flash memory device, including a cell array region where a plurality of memory cells are connected in series to a single cell string, the cell array region including a pocket p-well configured to accommodate the plurality of memory cells and an n-well configured to surround the pocket p-well, a first peripheral region where low-voltage (LV) and high-voltage (HV) switches are connected to the memory cells through a word line, and a second peripheral region where bulk voltage switches are connected to bulk regions of the LV and HV switches.

Flash memory device having triple well structure

A method of forming a semiconductor device pattern, a method of forming a charge storage pattern, a non-volatile memory device including a charge storage pattern and a method of manufacturing the same are provided. The method of forming the charge storage pattern including forming a trench on a substrate, and a device isolation pattern in the trench. The device isolation pattern protrudes from a surface of the substrate such that an opening exposing the substrate is formed. A tunnel oxide layer is formed on the substrate in the opening. A preliminary charge storage pattern is formed on the tunnel oxide layer and the device isolation pattern by selective deposition of conductive materials. The preliminary charge storage pattern may be removed from the device isolation pattern. The preliminary charge storage pattern remains only on the tunnel oxide layer to form the charge storage pattern on the substrate.

Method of forming a pattern for a semiconductor device, method of forming a charge storage pattern using the same method, non-volatile memory device and methods of manufacturing the same

Growing community of inventors

Hwaseong-si, South Korea

Se-Jun Park