Hynix Semiconductor Inc.

Samsung Electronics Co., Ltd.

Skhynix Inc.

Se Jun Kim

Nam Kyeong Kim

Young Tae Jang

Jae Chul Om

Sung Ho Suh

Sang Hoon Hong

Jong Hee Han

Hyun Jun Jung

Jin Ho Seo

Seog Heon Ham

Eun Seok Choi

Yong Jin Kim

Sung Soo Jung

Woo Sung In

Jeong Roh Lee

Doo Soon Park

Byung Jo Kim

Byung Joo Paek

Hyun Seung Yoo

Woo Young Kan

Kyoung Hwan Park

Weon Hee Lee

Jong Pil Seo

Sung-Il Yang

Hee Youl Lee

Ki Hong Lee

Jung Ryul Ahn

Sang Bum Lee

Yong Jae Park

Chun Seok Jeong

Yoo Nam Jeon

Hyeok Jong Lee

Ki Seon Park

Sun Mi Park

Young Ok Hong

Won Sic Woo

Moon Sig Joo

Kyung Pil Hwang

Myung Shik Lee

Jae Il Tak

Hea Jong Yang

Kyung Sik Mun

Soon Ok Seo

Jae Kyung Wee

Won Baek Lee

Yong Top Kim

Jeong Hoon Kook

Dae Jong Jong Kang

Kyung Hwan Park

Jae Young Park

Dae Jong Kang

An image sensor includes a pixel array and N analog-to-digital converters (ADCs). The pixel array includes N pixels arranged in each of a plurality of rows, and each of the N pixels include M photoelectric conversion elements. At least one of the N ADCs are shared by at least one of the M photoelectric conversion elements included in each of the N pixels.

Image sensor, data processing system including the same

An image sensor operating in a skip mode and reading out a pixel signal provided by at least one of a plurality of pixels and compensating for fixed pattern noise (FPN) in column-parallel pipelines. The image sensor includes; a switch signal generator that generates a first switch control signal and a second switch control signal in response to FPN location information characterizing a first pipeline among the column-parallel pipelines as a noisy pipeline generating FPN, and characterizing a second pipeline among the column-parallel pipelines as a quiet pipeline not generating FPN, a binning switch block including a first switch controlled by the first switch control signal and a second switch controlled by the second switch control signal, wherein the first switch control signal causes the first pipeline to be inactivated and the second switch control signal causes the second pipeline to be activated, and a binning block that performs a digital binning operation on digital signals provided via the column-parallel pipelines including the second pipeline.

Image sensor and image processing system that compensate for fixed pattern noise (FPN)

An image sensor which operates in a global shutter mode is provided. The image sensor includes a pixel array comprising a plurality of pixels arranged in a plurality of rows and columns, a timing generator configured to generate row driver control signals which controls an integration period of a pixel of the plurality of pixels to include at least two sub integration periods, and a row driver configured to generate a plurality of row control signals which controls each of the rows in the pixel array based on the row driver control signals, wherein the timing generator is further configured to control a single image frame to include the integration period and a readout period of the pixel, based on the row driver control signals.

Image sensor and image processing system including the same

A semiconductor device includes a plurality of electrically coupled memory cells in a generally vertical configuration extending in a generally perpendicular direction from a semiconductor substrate, a peripheral circuit configured to program the memory cells, and a control circuit configured to program a memory cell selected from the plurality of memory cells to trap charge in the selected memory cell, and to issue at least one command to the peripheral circuit to manage a dispersion of at least a portion of the trapped charge between memory cells adjacent to the selected memory cell.

Semiconductor device and programming method thereof

A display apparatus including a main body, a display panel installed in the main body, a video call unit installed to the main body, a circuit board for control of the video call unit, and a cable to connect the video call unit and the circuit board to each other, is provided. Installing the video call unit to the main body enables a video call via the display apparatus.

Display Apparatus

A method of operating a non-volatile memory device includes erasing a memory cell block, supplying a first drain turn-on voltage higher than a target level to the drain select line of the memory cell block, and performing a soft program operation by supplying a soft program voltage to the word lines of the memory cell block.

Method of operating non-volatile memory device

The semiconductor device includes a CAM block including a plurality of vertical strings having a perpendicular configuration with respect to a semiconductor substrate, wherein each of the plurality of vertical strings is electrically coupled to a plurality of word lines and each of the plurality of word lines is electrically coupled to a plurality of CAM cells, a peripheral circuit configured to program CAM cells selected from the plurality of CAM cells, and a control circuit configured to issue at least one command to the peripheral circuit to simultaneously apply a program voltage to an nword line, an n&#x2212;1word line and an n+1word line to simultaneously program CAM cells electrically coupled to the n&#x2212;1word line, the nword line and the n+1word line, wherein the n&#x2212;1word line and an n+1word line are adjacent to the nword line and the selected CAM cells are electrically coupled to the nword line.

Semiconductor device and operating method thereof

Display apparatus

A semiconductor memory device includes a plurality of memory blocks formed over a substrate including source regions and separated from each other by a slit, a plurality of bit lines coupled to the strings of the memory blocks and disposed over the memory blocks, and source contact lines formed within the slits, coupled to the source regions, respectively, and disposed in a direction to cross the plurality of bit lines.

Semiconductor memory device and method of manufacturing the same

A charge trap flash memory device is capable of preventing a data retention fail by ensuring a data retention margin. A method for operating the charge trap flash memory device is provided. A selected memory cell is programmed using a program voltage. The selected memory cell is verified using a first program verify voltage. Date retention states of selected memory cell having passed the program verify step are verified using a retention verify voltage. A read step of determining a program pass or fail by reading data of the selected memory cell having passed the retention verify step is performed using a read voltage.

Method for operating a flash memory device

A NAND flash memory device and method of manufacturing the same is disclosed. Source and drain select transistor gates are recessed lower than an active region of a semiconductor substrate. A valid channel length of the source and drain select transistor gates is longer than a channel length of memory cell gates. Accordingly, an electric field between a source region and a drain region of the select transistor can be reduced. It is thus possible to prevent program disturbance from occurring in edge memory cells adjacent to the source and drain select transistors in non-selected cell strings.

NAND flash memory device and method of manufacturing the same

A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.

Nonvolatile memory device and method of fabricating the same

A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.

Charge trap type non-volatile memory device and program method thereof

Growing community of inventors

Suwon-si, South Korea

Se Jun Kim