Samsung Electronics Co., Ltd.

Se-jin Jeong

Dong-Il Seo

Sei-seung Yoon

Chan-jong Park

Jin-man Han

Jung-hwa Lee

Il-man Bae

An internal clock signal generator of a synchronous memory device is provided. The internal clock signal generator includes first and second inverting portions, a delay portion, first and second switching portions, and first and second logic portions also called input and output logic circuits, respectively. The first inverting portion inverts an external clock signal. The second inverting portion inverts an output signal of the first inverting portion. The delay portion delays an output signal of the second inverting portion. The first switching portion gates an output signal of the delay portion in response to a first control signal. The second switching portion gates the output signal of the second inverting portion in response to a second control signal. The first or input logic portion performs a logic operation with respect to signals input from an external source and outputting the first and second control signals. The second or output logic portion receives a signal transmitted through a selected one of the first and second switching portions and the output signal from the first inverting portion, performs a logic operation with respect to the received signals, and outputs the internal clock signal.

Internal clock signal generator for synchronous memory device

There is disclosed a parallel test circuit for a semiconductor memory device having a memory army with a plurality of memory cells and a plurality of comparators used for high-speed memory cell test, including a plurality of fist comparators performing first comparison with respect to data transmitted through a plurality of data output lines formed near memory blocks of the memory array; a plurality of second comparators coupled in common with each output terminal of the first comparators and performing second comparison with respect to output data of the first comparators; a multiplexer multiplexing output of the second comparator; first and second switches alternatively connected to an output terminal of the multiplexer; and a data output buffer coupled in common with output terminals of the first and second switches and buffering outputs of the first and second switches. The multiplexer is connected to the first switches for a first mode operation, and is connected to the second switch for a second mode operation to thereby perform a two-way data test.

Parallel test circuit for semiconductor memory device

Address buffers of a semiconductor memory device have a switching section for switching into each other transmission routes of first and second address signals input from outside in response to predetermined control signals. The signals allow input of the address signals and set the operating mode of the semiconductor memory device.

Address buffers of semiconductor memory device

A semiconductor memory device architecture and method thereof obtains a high data bandwidth by forming multiple input/output lines. A unit array has a plurality of reference blocks formed in a length direction of the device, each reference block storing a plurality of memory cells. A sub array has a plurality of unit arrays formed in a longitudinal direction perpendicular to the length direction. A word line selects memory cells from within the reference blocks, the word line extending in the length direction. A pair of bit lines and a pair of data input/output lines extend in the longitudinal direction. The pair of data input/output lines are correspondingly connected to 2.sup.n (n=1,2, . . . ) pairs of bit lines. A read select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a read operation. A write select signal line selects a pair of bit lines from among 2.sup.n pairs of bit lines connected to one pair of data input/output lines in response to an input of a column address during a write operation. A column gate connects the pair of bit lines to the pair of data input/output lines. A column select line extends in the longitudinal direction and controls the column gate, and a pair of main data input/output lines are connected correspondingly through a multiplexer to a plurality of data input/output lines.

Layout method for semiconductor memory device obtaining high bandwidth

There is provided in the present invention a signal generator which generates a bit line equalization signal and a signal generator which generates a sense amplifier equalization signal to control the bit line equalization circuit and the sense amplifier equalization circuit, respectively. The generated bit line equalization signal and sense amplifier equalization signal both have a voltage level that is at least about equal to, and preferably greater than, an external power supply voltage. The signals generated by these signal generators can thus be used by operating voltages which are much less than was previously possible.

Sense amplifier circuit in semiconductor memory device

The present invention relates to a semiconductor memory device and more particularly to a semiconductor memory device and a method for arranging a signal line therein which can realize a high bandwidth by embodying a chip architecture being comprised of a multi I/O line. A semiconductor memory device includes arrays comprised of a plurality of reference blocks for storing a plurality of memory cells, a plurality of word lines extending in the direction of length of a chip, a plurality of bit lines extending in a vertical direction of length of a chip, each pair of bit lines being comprised of a bit line and a complementary bit line, a plurality of data I/O lines arranged on the upper portion of the arrays and extending in the vertical direction, each pair of data I/O lines being comprised of a data I/O line and a complementary data I/O line and being one by one connected to each pair of bit lines, and a plurality of column selection lines arranged in the vertical direction and adjacent to the data I/O line and complementary data I/O line, for controlling connection of each pair of bit lines to the data I/O lines.

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Seoul, South Korea

Se-jin Jeong