Samsung Electronics Co., Ltd.

Se-Hyeong Lee

Jun Hyuk Seo

Jong-Heui Song

O-Ik Kwon

Min-Woong Choi

A method of manufacturing a semiconductor device includes sequential steps of forming a gate insulating layer, a first conductive layer, an etch stop layer, a hard mask layer, and an anti-reflective layer on a semiconductor substrate. The anti-reflective layer, hard mask layer, and etch stop layer are then partially etched according to a pattern to create an anti-reflective layer pattern, hard mask layer pattern, and etch stop layer pattern. The anti-reflective layer can be formed of a porous plasma silicon oxinitride layer to keep irregular reflections to a minimum. The anti-reflective layer pattern is then etched, followed by an etching of the first conductive layer to form a gate electrode under the etch stop layer pattern. A conformal spacer insulating layer is formed on the whole surface of the semiconductor substrate, and an interlayer insulating layer is formed on the spacer insulating layer so as to fill openings between the gate electrodes. The interlayer insulating layer, the spacer insulating layer and the hard mask pattern are etched using the etch stop layer pattern as an etch mask, and thereby forming self-aligned contact holes exposing the semiconductor substrate between the gate electrodes.

Method of manufacturing a semiconductor device using anti-reflective layer and self-aligned contact technique and semiconductor device manufactured thereby

Provided is a method for fabricating a stacked capacitor with improved vertical and bottom etching profiles without electrical bridge between adjacent lower electrodes. Conductive layer for a lower electrode is deposited over an insulating layer whose top portion is made of a nitride etching barrier layer. During the etching of the conductive layer and subsequent overetching for lower electrode pattern, the nitride etching barrier layer serves an etching stopper and allows easier formation of polymer buildups on sidewalls of the lower electrode, more particularly on a bottom edge thereof. Resulting polymer buildups serve to prevent unacceptable bottom and sidewall etching of the lower electrode.

Method for fabricating a DRAM cell capacitor including etching upper conductive layer with etching byproduct forming an etch barrier on the conductive pattern

A cylindrical storage capacitor for a memory cell is disclosed. The cylindrical storage capacitor has a first polysilicon layer for a storage electrode in contact with conductive plug, the first polysilicon layer being a cylindrical structure, and having a hemispherical grain silicon (HGS) grown only at inner and top surfaces of the first polycrystalline silicon layer. The HGS widens the effective surface area of the storage electrode, to thereby secure a target capacitance and prevent adjacent storage capacitors from being micro-bridged. Moreover, the cylindrical first polysilicon pattern layer of which the outer peripheral surface have a fine vertical profile can be obtained by applying the nitride film as an etch stopper when forming the opening part in a selected portion of the first insulating layer.

Methods of forming integrated circuit capacitors having merged annular storage electrodes therein

A multiple tubular shaped capacitor electrode of a semiconductor capacitor with an increased surface area and a method for fabricating thereof. The multiple tubular shaped capacitor includes at least two tubular shapes whose side portions are overlapped with each other. The multiple tubular shaped capacitor is made by forming an insulating layer over an etch stop layer including a contact plug, partially etching the insulating layer down to the contact plug and etch stop layer to form an opening composed of at least two upright cylindrical openings with side portions that define an overlap, and forming a conductive layer on a bottom and both side walls of the opening to form a storage node composed of at least two upright tubular shapes which are attached together at a vertical side section which defines an overlap portion of both tubular shapes to form a capacitor storage node.

Capacitor and method for fabricating the same

A plasma etching apparatus is provided having a sealing member coupling an upper electrode to the plasma etching chamber. A peripheral portion of the inner surface of the upper electrode includes a planar surface across both anodized and non-anodized portions of the surface in the peripheral contact region adjacent to the upper portion of the sidewalls of the chamber assembly. A sealing member is positioned between the planar, peripheral portion of the second electrode and the upper portion of the sidewalls to provide a seal therebetween. The anodized portion of the inner surface of the upper electrode may extend over the area adjacent to the opening in the chamber housing and further extend into the peripheral portion beyond the sealing member to reduce the potential for arcing to occur to the non-anodized section during plasma etching operations. Plasma etching apparatus according to the present invention may provide improved sealing, thereby allowing improved control of vacuum level and concentration of processing gas within the plasma etching chamber during etching operations.

Growing community of inventors

Sungnam-shi, South Korea

Se-Hyeong Lee