Samsung Electronics Co., Ltd.

Se-Hoon Oh

Jung-Hoon Kim

Jong-Hyun Shin

Sung-Tae Kim

Cha-young Yoo

Jae-hyoung Choi

Jung-hee Chung

Jeong-sik Choi

Han-jin Lim

Young-Sun Kim

Eun-ha Lee

Kwang-Hee Lee

Wan-Don Kim

Sun-Jung Kim

Young-Su Chung

Display screen or portion thereof with graphical user interface

Display screen or portion thereof with transitional graphical user interface

Display screen or portion thereof with icon

In one aspect, a memory cell includes a plurality of dielectric layers located within a charge storage gate structure. At least one of the dielectric layers includes an dielectric material including oxygen, and nano regions including oxygen embedded in the dielectric material, where an oxygen concentration of the dielectric material is the greater than an oxygen concentration of the nano regions. In another aspect, at least one of the dielectric layers includes a dielectric material and nano regions embedded in the dielectric material, where an atomic composition of the dielectric material is the same as the atomic composition of the nano regions, and a density of the dielectric material is the greater than a density of the nano regions.

Memory devices comprising nano region embedded dielectric layers

Integrated circuit devices, for example, dynamic random access memory (DRAM) devices, are provided including an integrated circuit substrate having a cell array region and a peripheral circuit region. A buried contact plug is provided on the integrated circuit substrate in the cell array region and a resistor is provided on the integrated circuit substrate in the peripheral circuit region. A first pad contact plug is provided on the buried contact plug in the cell array region and a second pad contact plug is provided on the resistor in the peripheral circuit region. An ohmic layer is provided between the first pad contact plug and the buried contact plug and between the second pad contact plug and the resistor. Related methods of fabricating integrated circuit devices are also provided.

Integrated circuit devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

Methods of forming integrated circuits devices having pad contact plugs in the cell array and peripheral circuit regions of the integrated circuit substrate

A lower electrode is formed from a first metal on a semiconductor substrate. Atoms of a second metal, that is different than the first metal, are diffused into the lower electrode. A dielectric layer is formed on the lower electrode, and an upper electrode is formed on the dielectric layer. Diffusion of second metal atoms into the lower electrode may reduce or prevent crystal grain growth and agglomeration on a surface of the lower electrode during a subsequent high temperature process.

Methods for manufacturing semiconductor memory devices

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Seoul, South Korea

Se-Hoon Oh