Samsung Electronics Co., Ltd.

Se-hoon Oh

Jae-hyoung Choi

Cha-young Yoo

Jung-hee Chung

Young-sun Kim

Han-Mei Choi

Jong-Cheol Lee

Youn-soo Kim

Jeong-sik Choi

Young-Geun Park

Sung-Tae Kim

Ki-chul Kim

Yong-jae Lee

Han-jin Lim

Seung-hwan Lee

Ki-Vin Im

Cha-Young Yoo

Ki-yeon Park

Hyun-jun Kim

Sun-jung Kim

Hoon-Sang Choi

Sun-Min Moon

Jin-sun Lee

Seung-Hwan Lee

Seok-Jun Won

Yong-Kuk Jeong

Myoung-Bum Lee

Woo-Gwan Shim

Ki-Yeon Park

Dae-Jin Kwon

Sang-Yeol Kang

Jeong-hee Chung

Sun-Jung Kim

Kyong-Won An

Dong-chul Yoo

Jung-Hee Chung

Nam-Myun Cho

Min-kyung Ryu

Byong-ju Kim

Seon-ho Jo

Hong-bum Park

Dong-kyun Park

A method of forming a material layer includes providing a substrate into a reaction chamber, providing a source material onto a substrate, the source material being a precursor of a metal or semimetal having a ligand, providing an ether-based modifier on the substrate, purging an inside of the reaction chamber, and reacting a reaction material with the source material to form the material layer.

Methods of forming material layer

Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

Methods of forming integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

Provided are methods of removing water adsorbed or bonded to a surface of a semiconductor substrate, and methods of depositing an atomic layer using the method of removing water described herein. The method of removing water includes applying a chemical solvent to the surface of a semiconductor substrate, and removing the chemical solvent from the surface of the semiconductor substrate.

Methods of removing water from semiconductor substrates and methods of depositing atomic layers using the same

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions and methods of forming same

A capacitor includes a substrate, a plurality of first storage electrodes, a plurality of second storage electrodes, a first supporting layer pattern, a dielectric layer and a plate electrode. A plurality of contact pads is formed I the substrate. The first storage electrodes are arranged along lines parallel with a first direction and electrically connected to the contact pads, respectively. The second storage electrodes are respectively stacked on the first storage electrodes. The first supporting layer pattern extends in a direction parallel with the first direction between adjacent second storage electrodes and makes contact with the adjacent second storage electrodes to support the second storage electrodes. The dielectric layer is formed on the first and second storage electrodes. The plate electrode is formed on the dielectric layer.

Capacitor

Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer are provided, the methods of forming the metal silicate layer include forming the metal silicate using a plurality of silicon precursors. The silicon precursors are homoleptic silicon precursors in which ligands bound to silicon have the same molecular structure.

Methods of forming a metal silicate layer and methods of fabricating a semiconductor device including the metal silicate layer

Capacitors having composite dielectric layers containing crystallization inhibiting regions

A method of forming a flash memory device can include forming a tunneling oxide film on a semiconductor substrate, forming a charge storing layer on the tunneling oxide film, forming a first blocking oxide film on the charge storing layer at a first temperature, forming a second blocking oxide film on the first blocking oxide film at a second temperature higher than the first temperature, and forming a gate electrode on the second blocking oxide film.

Methods of forming flash memory devices including blocking oxide films

Methods of manufacturing a semiconductor device are provided including forming a charge storage layer on a gate insulating layer that is on a semiconductor substrate. A blocking insulating layer is formed on the charge storage layer and an electrode layer is formed on the blocking insulating layer. The blocking insulating layer may be formed by forming a lower metal oxide layer at a first temperature and forming an upper metal oxide layer on the lower metal oxide layer at a second temperature, lower than the first temperature.

Methods of manufacturing semiconductor devices including metal oxide layers

Integrated circuit capacitors having composite dielectric layers therein containing crystallization inhibiting regions

A method of manufacturing a non-volatile memory device includes forming a tunnel isolation layer forming a tunnel isolation layer on a substrate, forming a conductive pattern on the tunnel isolation layer, forming a lower silicon oxide layer on the conductive pattern, treating a surface portion of the lower silicon oxide layer with a nitridation treatment to form a first silicon oxynitride layer on the lower silicon oxide layer, forming a metal oxide layer on the first silicon oxynitride layer, forming an upper silicon oxide layer on the metal oxide layer, and forming a conductive layer on the upper silicon oxide layer.

Method of manufacturing a non-volatile memory device

In a non-volatile memory device and a method of manufacturing the non-volatile memory device, a tunnel insulating layer, a charge trapping layer, a dielectric layer and a conductive layer may be sequentially formed on a channel region of a substrate. The conductive layer may be patterned to form a gate electrode and spacers may be formed on sidewalls of the gate electrode. A dielectric layer pattern, a charge trapping layer pattern, and a tunnel insulating layer pattern may be formed on the channel region by an anisotropic etching process using the spacers as an etch mask. Sidewalls of the charge trapping layer pattern may be removed by an isotropic etching process to reduce the width thereof. Thus, the likelihood of lateral diffusion of electrons may be reduced or prevented in the charge trapping layer pattern and high temperature stress characteristics of the non-volatile memory device may be improved.

Non-volatile memory device and method of manufacturing the same

Provided are methods of manufacturing dielectric films including forming a first dielectric film on a wafer using atomic layer deposition (ALD) in a first batch type apparatus, forming a second dielectric film on the first dielectric film using atomic layer deposition in a second batch type apparatus, wherein the second dielectric film has a higher crystallization temperature than the first dielectric film and forming a third dielectric film on the second dielectric film using atomic layer deposition in a third batch type apparatus. Methods of manufacturing metal-insulator-metal (MIM) capacitors using the methods of forming the dielectric films and batch type atomic layer deposition apparatus for forming the dielectric films are also provided.

Methods and batch type atomic layer deposition apparatus for forming dielectric films and methods of manufacturing metal-insulator-metal capacitors including the dielectric films

Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

Semiconductor device capacitors with oxide-nitride layers and methods of fabricating such capacitors

Growing community of inventors

Gyeonggi-do, South Korea

Se-hoon Oh