Skhynix Inc.

Other

Hynix Semiconductor Inc.

Se Hoon Kim

Jung Ryul Ahn

Eun Seok Choi

Jung Seok Oh

In Geun Lim

Yong Dae Park

Hee Youl Lee

Ji Hyun Seo

Dong Hun Lee

Jun Woo Kim

Jung Shik Jang

Tae Gyun Kim

Su Won Cho

Provided herein may be a semiconductor device and a method of operating a semiconductor device. The method may include: performing a first program operation on a selected memory cell using a first program pulse, a first bit line voltage, a first pre-verify voltage, and a first main verify voltage, with a first level difference between the first pre-verify voltage and the first main verify voltage; and performing a second program operation on the selected memory cell using a second program pulse, a second bit line voltage, a second pre-verify voltage, and a second main verify voltage, with a second level difference between the second pre-verify voltage and the second main verify voltage. The second level difference may be less than the first level difference, and the second bit line voltage may have a level higher than a level of the first bit line voltage.

Semiconductor device and method of operating semiconductor device

Disclosed herein are an elastic encoder and manufacturing method thereof. The elastic encoder of the present invention includes a reinforcing rim which has a reinforcing body and a reinforcing flange formed along a peripheral part of the reinforcing body and which is manufactured using a metallic material; and a plastic magnet which is bound to the reinforcing flange so as to surround the reinforcing flange, includes synthetic resin, rubber material, and magnetic powder, and has a plurality of magnetic poles magnetized in a circumferential direction.

Elastic encoder and manufacturing method thereof

Provided is a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory unit including a plurality of memory blocks; a voltage supply circuit configured to generate a plurality of operating voltages and output the generated operating voltages to at least two global line groups during a program operation on the memory unit; a pass circuit configured to couple word lines of the memory blocks to the at least two global line groups; and a control logic configured to control the voltage supply circuit and the pass circuit such that during a program verify operation of the program operation, a program verify voltage is applied to a selected memory block of the memory blocks, and a set voltage is applied to a share memory block sharing with the selected memory block among unselected memory blocks.

Semiconductor memory device and method of operating the same

A semiconductor memory device is operated by, inter alia, performing least significant bit programs for pages in a first page group, performing least significant bit programs for pages in a second page group, and performing most significant bit programs for the pages in the first page group. The distance between the second page group and the common source line is greater than that between the first page group and the common source line.

Provided are a semiconductor memory device and an operating method thereof. The semiconductor memory device may include a memory cell array having a plurality of strings each including a drain select transistor, a plurality of drain side memory cells, a pipe transistor, a plurality of source side memory cells, and a source select transistor. The semiconductor memory device may also include a peripheral circuit suitable for providing a plurality of operation voltages including an erase verify voltage to the plurality of strings, and a control logic suitable for controlling the peripheral circuit to adjust a voltage level of the erase verify voltage applied to a selected memory cell, from among the plurality of drain side memory cells and the plurality of source side memory cells, according to a distance between the selected memory cell and the pipe transistor when an erase verify operation is performed.

Semiconductor memory device and operating method thereof

A semiconductor memory device and an operating method thereof are provided. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; and a peripheral circuit programming first, second, third, and fourth memory cells connected to one word line and successively arranged, among the plurality of memory cells, wherein the peripheral circuit is configured to program the first and fourth memory cells in a first interval and program the second and third memory cells in a second interval. A semiconductor memory device having enhanced performance characteristics and an operating method thereof are provided.

Semiconductor device and operating method thereof

A three-dimensional (3-D) non-volatile memory device according to embodiment of the present invention includes a plurality of bit lines, at least one string row extending in a first direction coupled to the bit lines and including 2N strings, wherein the N includes a natural number, a common source selection line configured to control source selection transistors of the 2N strings included in a memory block, a first common drain selection line configured to control drain selection transistors of a first string and a 2N-th string among the 2N strings included in a memory block, and N&#x2212;1 second common drain selection lines configured to control drain selection transistors of adjacent strings in the first direction among remaining strings other than the first string and the 2N-th string.

Three-dimensional non-volatile memory device

A method of manufacturing a non-volatile memory device includes forming a conductive layer to form a gate on a semiconductor substrate; forming a hard mask over the conductive layer; patterning the hard mask and the conductive layer of a cell region to form the gate; partially recessing the hard mask using a mask through which a peripheral region is opened; and patterning the recessed hard mask and the conductive layer of the peripheral region to form the gate.

Growing community of inventors

Changwon-si, South Korea

Se Hoon Kim