Samsung Electronics Co., Ltd.

Se-Chung Oh

Jang-Eun Lee

Hyun-Jo Kim

Kyung-Tae Nam

Kyung-tae Nam

Jun-Ho Jeong

Jun-Soo Bae

Yong-Sung Park

In-gyu Baek

Woo-Jin Kim

Joon-Myoung Lee

Jeong-Heon Park

Young-Ki Ha

Ju-hyun Kim

Jun-ho Jeong

In-Gyu Baek

Ki-woong Kim

Hee-Ju Shin

Dae-Kyom Kim

Hyun Min Cho

Jae-Hoon Kim

Kee-won Kim

Young-Man Jang

Hyun-Jun Sim

Jung-hwan Park

Whan-Kyun Kim

Yun-Jae Lee

Jin-Shi Zhao

Dong-kyu Lee

Eun-Kyung Yim

Woo-chang Lim

Kyung-il Hong

Jung-min Lee

Hyung-Rok Oh

Byoung-Jae Bae

Jong-Chul Park

Suk-Hun Choi

Young-Hyun Kim

Seung-yeol Lee

Ki-Woong Kim

Jea-Hyoung Lee

Jun-Ho Jeon

A substrate processing apparatus including a chamber accommodating a substrate; a substrate support in the chamber, the substrate support supporting the substrate; a gas injector to inject an oxidizing gas for oxidizing a metal layer to be disposed on the substrate; a cooler under the substrate to cool the substrate; a target mount disposed on the substrate, the target mount including a target for performing a sputtering process; and a blocker between the target and the gas injector, the blocker shielding the target from the oxidizing gas injected from the gas injector.

Substrate processing apparatus

The methods of manufacturing an MRAM device and MRAM devices are provided. The methods may include forming a first electrode on an upper surface of a substrate, forming a first magnetic layer on the first electrode, forming a tunnel barrier structure on the first magnetic layer, forming a second magnetic layer on the tunnel barrier structure, and forming a second electrode on the second magnetic layer. The tunnel barrier structure may include a first tunnel barrier layer and a second tunnel barrier layer that are sequentially stacked on the first magnetic layer and may have different resistivity distributions from each other along a horizontal direction that may be parallel to the upper surface of the substrate.

Magnetoresistive random access memory devices and methods of manufacturing the same

A variable resistance memory device includes a metal interconnection layer on a substrate, an interlayer insulating layer on the metal interconnection layer and defining a contact hole for exposing a portion of the metal interconnection layer, a barrier metal layer including a plurality of sub-barrier metal layers inside the contact hole, a plug metal layer on the barrier metal layer and burying the contact hole, and a variable resistance structure on the barrier metal layer and the plug metal layer.

Variable resistance memory device

In a method of manufacturing a variable resistance memory device, an MTJ structure layer is formed on a substrate. The MTJ structure layer is etched in an etching chamber to form an MTJ structure. The substrate having the MTJ structure thereon is transferred to a deposition chamber through a transfer chamber. A protection layer covering a sidewall of the MTJ structure is formed in the deposition chamber. The etching chamber, the transfer chamber, and the deposition chamber are kept in a high vacuum state equal to or more than about 10Torr.

Method of manufacturing a variable resistance memory device

Substrate processing apparatus and method for manufacturing semiconductor device using the same

A magnetic device includes a free layer; a pinned layer; a tunnel barrier disposed between the free layer and the pinned layer; a polarization enhancement layer disposed between the tunnel barrier and the pinned layer; and a blocking layer disposed between the polarization enhancement layer and the pinned layer, wherein the blocking layer includes a first diffusion trap layer and a second diffusion trap layer disposed on the first diffusion trap layer.

Magnetic device

A method of fabricating a memory device, the method including forming a first magnetization layer; forming a tunnel barrier layer on the first magnetization layer; forming a second magnetization layer on the tunnel barrier layer; forming a magnetic tunnel junction (MTJ) structure by patterning the first magnetization layer, the tunnel barrier layer, and the second magnetization layer; and forming a boron oxide in a sidewall of the MTJ structure by implanting boron.

Method of fabricating memory device

A magnetic memory device includes a substrate, a circuit device on the substrate, a lower electrode electrically connected to the circuit device, a magnetic tunnel junction structure (MTJ structure) on the lower electrode, and an upper electrode on the MTJ structure. The MTJ structure includes a pinned layer structure including at least one crystalline ferromagnetic layer and at least one amorphous ferromagnetic layer, a free layer, and a tunnel barrier layer between the pinned layer structure and the free layer.

Magnetic memory devices

A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Semiconductor device having pinned layer with enhanced thermal endurance

A nonvolatile memory device includes a bottom electrode on a semiconductor substrate, a data storage layer on the bottom electrode, the data storage layer including a transition metal oxide, and a switching layer provided on a top surface and/or a bottom surface of the data storage layer, wherein a bond energy of material included in the switching layer and oxygen is more than a bond energy of a transition metal in the transition metal oxide and oxygen.

Nonvolatile memory devices and methods of forming the same

Provided is a stacked magnetic random access memory (MRAM) in which memory cell arrays having various characteristics or functions are included in memory cell layers. The stacked MRAM device includes a semiconductor substrate and at least one memory cell layers. The semiconductor substrate includes a first memory cell array. Each of the memory cell layers includes a memory cell array having a different function from the first memory cell array and is stacked on the first memory cell array. As a result, the stacked MRAM device has high density, high performance, and high reliability.

Stacked MRAM device and memory system having the same

A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.

Method for forming magnetic tunnel junction structure and method for forming magnetic random access memory using the same

Growing community of inventors

Gyeonggi-do, South Korea

Se-Chung Oh