Integrated Device Technology, Inc.

Other

Netlogic Microsystems, Inc

Scott Yu-Fan Chu

Kee W Park

Robert J Proebsting

Michael J Miller

Chuen-Der Lien

Chau-Chin Wu

Mark W Baumann

Bertan Tezcan

Kenneth Branth

Thomas Diede

Chuen Der Lien

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The priorities of multiple CAM array blocks within the CAM device may be programmed before or as entries are loaded therein and may be reprogrammed during operation as the allocation of entries within the CAM device changes. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include preferred priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority. This aspect of the priority resolution circuit is provided so that an active hit signal having a highest overall priority can be resolved whenever multiple CAM array blocks having the same soft priority are detected as having matching entries therein during a search operation.

Content addressable memory (CAM) devices having soft priority resolution circuits therein and methods of operating same

Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit. The control circuit, which is electrically coupled to the plurality of CAM array blocks, is configured to perform built-in self repair (BISR) of hard memory defects and/or compare logic defects in the plurality of CAM array blocks concurrently with operations to search entries in the plurality of CAM array blocks.

Content addressable memory (CAM) devices that support background BIST and BISR operations and methods of operating same

A CAM array has at least one row therein containing a plurality of memory cells with different susceptibilities to soft errors. The memory cells having reduced susceptibilities to soft errors include those used in check bit cells and/or CAM cells containing valid bit data and/or force no-hit data. Additional memory cells may also be provided with somewhat greater susceptibilities to soft errors and somewhat more aggressive design rules (e.g., smaller layout area). These additional memory cells may include those used in ternary CAM cells (e.g., XY CAM cells) within the row.

Content addressable memory (CAM) arrays having memory cells therein with different susceptibilities to soft errors

Content addressable memory (CAM) devices use both hard and soft priority techniques to allocate entries of different priority therein. The allocation of entries may change in response to additions or deletions of entries or as entries are reprioritized. The CAM devices include priority resolution circuits that can resolve competing soft and hard priorities between multiple hit signals that are generated in response to a search operation. Such hit signals may be active to reflect the presence of at least one matching entry within a CAM array block. The resolution of which active hit signal has the highest overall priority among many can be used to facilitate the identification of the location (e.g., array address and row address) of a highest priority matching entry within the entire CAM device. A priority resolution circuit may also resolve competing hard priorities between two or more active hit signals having equivalent soft priority.

Multi-bank content addressable memory (CAM) devices having staged segment-to-segment soft and hard priority resolution circuits therein and methods of operating same

Content addressable memory (CAM) devices include at least one CAM array having a plurality of columns of ternary CAM cells therein. A bit/data line driver circuit, which receives search words and write words, is electrically coupled to the CAM array. The bit/data line driver circuit is configured to save power by logically combining incoming search words with a global mask that designates locations of active ones of the plurality of columns having exclusively locally masked CAM cells at valid entries therein. The bit/data line driver circuit includes a global mask generator configured to receive write words to be added to the CAM array during respective write operations.

Content addressable memory (CAM) devices that support power saving longest prefix match operations and methods of operating same

Search engine devices include a content addressable memory (CAM) core having a plurality of CAM array blocks therein and a control circuit that is electrically coupled to the CAM core. The control circuit is configured to support internal error detection and correction operations using modified Hamming code words. These operations are performed without significant impact on the compare bandwidth of the search engine device, even when operations to read entries from the CAM core are performed as foreground operations that may block concurrent search operations. The control circuit may perform the error detection and correction operations by issuing multiple read instructions. These instructions include a first instruction (e.g., error check instruction) to read at least a first entry into the CAM core for the purpose of error detection and then, in response to detecting the first entry as erroneous, issuing a second instruction to read the first entry from the CAM core. The entry is then corrected and written back into the CAM core.

Content addressable memory (CAM) devices having multi-block error detection logic and entry selective error correction logic therein

A CAM array block is configured to perform a search operation in a staged segment-to-segment manner using a plurality of hybrid comparands that are pipelined into the CAM array block during consecutive stages of the search operation. These hybrid comparands include at least a virtual sector field and a data field. The CAM array block is also responsive to a segment address, which identifies an active segment of CAM cells in said CAM array block. The CAM array block may include a CAM array and a global mask cell sub-array that is electrically coupled to the CAM array. This global mask cell sub-array may be responsive to the segment address and a mode select signal. A bit/data line control circuit is also provided. The bit/data line control circuit is electrically coupled to the CAM array by bit lines and data lines and has inputs that are responsive to signals generated by the global mask cell sub-array. The device may also include an address translation unit that is responsive to an input address. This address translation unit may be a RAM device that receives a second portion of an input address as a read address. The RAM device may generate at least the virtual sector field and the segment address.

Content addressable memory (CAM) devices with block select and pipelined virtual sector look-up control and methods of operating same

CAM devices include a segmented CAM array that is configured to support a long word search operation (e.g., x8N search) as a plurality of overlapping segment-to-segment search operations that are each performed across different rows within a group of rows in the CAM array and staggered in time relative to one another. To provide enhanced soft error immunity, these CAM devices may also include a CAM array having a row of lateral XY TCAM cells therein that are arranged in a repeating low-even, low-odd, high-even, high-odd sequence, where 'low' and 'high' represent the first and second halves of a CAM entry. Methods of operating a CAM device may include staggering the timing of overlapping segment-to-segment search operations across different rows within a CAM array using force-to-miss control signals to establish miss conditions on match lines of rows that are not to participate in a respective ones of the segment-to-segment search operations.

Content addressable memory (CAM) devices that utilize segmented match lines and word lines to support pipelined search and write operations and methods of operating same

Segmented CAM arrays are provided with dual-capture match line signal repeaters that support high speed pipelined search operations. A dual-capture match line signal repeater may extend between xR and xS segments of CAM cells within a respective row. This repeater provides high speed operation by quickly accessing the state (match or miss) of a match line segment when a corresponding segment of CAM cells connected to the match line segment undergo a respective stage of a pipelined search operation. If the match line segment is initially assessed as having a match signal thereon, then that match signal is passed to a next higher match line segment within the same row and a next stage search operation is commenced. However, if the match line segment is erroneously assessed as having a match signal thereon, when a miss condition was actually present in the corresponding segment of CAM cells, then the signal repeater will operate to capture a late miss signal and pass that late miss signal to the next higher match line segment to correct an error.

Content addressable memory (CAM) devices that utilize dual-capture match line signal repeaters to achieve desired speed/power tradeoff and methods of operating same

Multi-bank content addressable memory (CAM) devices having segment-based priority resolution circuits therein and methods operating same

Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.

Content addressable and random access memory devices having high-speed sense amplifiers therein with low power consumption requirements

Content addressable memory (CAM) devices achieve high integration by utilizing one or more CAM arrays that are each partitioned by rows into a CAM cell sub-array and a dedicated mask cell sub-array. Each row of mask cells within the mask cell sub-array can be selectively read during one search operation and then used to globally mask one or more columns of the CAM cell sub-array during a following search operation. Mask assertion circuitry is provided to couple a respective mask cell sub-array to a bit/data line control circuit that drives bit and/or data lines to the CAM cell sub-array during read, write and search operations. The mask cell sub-array and CAM cell sub-array may be segmented arrays that support pipelined search, write and read mask operations.

Content addressable memory (CAM) devices having dedicated mask cell sub-arrays therein and methods of operating same

Content addressable memory (CAM) devices according to embodiments of the present invention conserve match line and bit line power when CAM array blocks therein are searched. These CAM array blocks are searched in a pipelined segment-to-segment manner to increase search speed. The pipelined search operations may also be interleaved with write and read operations in an efficient manner that reduces the occurrence of pipeline bubbles.

Content addressable memory (CAM) devices having CAM array blocks therein that perform pipelined and interleaved search, write and read operations and methods of operating same

Content addressable memory (CAM) devices having CAM array blocks therein that conserve bit line power during staged compare operations

Content addressable memory (CAM) devices include a first match line segment associated with a first row of CAM cells within a CAM array and an inverter having an input electrically coupled to the first match line segment. A match line precharge support circuit is provided. The match line precharge support circuit includes a first PMOS transistor having a gate terminal electrically coupled to an output of the inverter, a first current carrying terminal that is electrically coupled to the first match line segment and a second current carrying terminal that is electrically coupled to a power supply line.

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San Jose, CA, United States of America

Scott Yu-Fan Chu