3com Corporation

Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Hewlett Packard Enterprise Development LP

Scott William Mitchell

Chi-Lie Wang

BaoDong Hu

Lawrence M Burns

Ngo Thanh Ho

Tan Thanh Ho

Baranitharan Subbiah

Kap Soh

George Kwan

Andrew Nakao

Sudhakar Rao

Lomberto P Jimenez

Sanjay Katabathuni

Shoby A Cherian

Maria Hu

Raymond Su

Ryan E Hirth

David A Fisher

Chong Woo

Ravi Ramachandran

Bruce Kendall

A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in to which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.

Computer system and network interface with hardware based packet filtering and classification

A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.

Computer system and network interface supporting class of service queues

A data processing system adapted for high-speed network communications, a method for managing a network interface and a network interface for such system, are provided, in which processing of packets received over the network is achieved by embedded logic at the network interface level. Incoming packets on the network interface are parsed and classified as they are stored in a buffer memory. Functional logic coupled to the buffer memory on the network interface is enabled to access any data field within a packet in a single cycle, using pointers and packet classification information produced by the parsing and classifying step. Results of operations on the data fields in the packets are available before the packets are transferred out of the buffer memory. A data processing system, a method for management of a network interface and a network interface are also provided by the present invention that include an embedded firewall at the network interface level of the system, which protects against inside and-outside attacks on the security of data processing system. Furthermore, a data processing system, a method for management of a network interface and a network interface are a provided by the present invention that support class of service management for packets incoming from the network, by applying priority rules at the network interface level of the system.

In one embodiment of a networking module, a first block receives a serial digital media signal, and provides a parallel digital media signal based on the serial digital media signal. A second block, operative with the first block, stores the parallel digital media signal in a corresponding slot in an outgoing frame, and sends the outgoing frame in response to receiving an incoming frame.

Method and apparatus for real-time transport of multi-media information in a network

Computer system and network interface with hardware based rule checking for embedded firewall

A network interface comprises the first port on which incoming data is transmitted and received at the data transfer rate of the network, a buffer memory coupled to the first port, and a second port coupled with the buffer memory, and through which transfer of packets between the host system, and the buffer memory is executed. A driver in the host system allocates a plurality of sets of receive buffers, where each set of receive buffers is composed of receive buffers having different sizes. A receive buffer descriptor cache located at the interface level stores receive buffer descriptors corresponding to receive buffers in the plurality of sets. As incoming packets arrive at the interface, logic determines the size of the incoming packet and assigns the packet to a receive buffer descriptor in the receive buffer descriptor cache according to the determined size. Upload logic at the interface level manages the uploading of packets from the buffer memory to the host system using the assigned receive buffer descriptors. A driver in the host dynamically adjusts the sizes of receive buffers in response to statistics about packet size.

Computer system and network interface supporting dynamically optimized receive buffer queues

In a system that demodulates a frequency modulated signal using a quadrature detector circuit, an apparatus that tunes the output signal to compensate for any offset in the signal includes an offset adjustment circuit and a control circuit. The offset adjustment circuit is operably coupled to the control circuit which may consist of a DAC and a digital logic such as a computer CPU. The control circuit determines a correction signal in response to a sequence of sampled of the system output, and supplies the correction signal to the offset adjustment circuit. The offset adjustment circuit provides an offset correction signal in response to the correction signal, and combines the offset correction signal with the output of the quadrature detector to provide an offset adjusted signal at an output node.

Dynamic adjustment to preserve signal-to-noise ratio in a quadrature detector system

A circuit and method thereof for arbitrating between a first power source and a second power source in a computer system peripheral device such as a network adapter (e.g., a network interface card) that is connected to multiple power sources. The circuit includes a field effect transistor (FET) and a diode integral with the FET coupled between the first power source and the second power source. The FET is adapted to conduct current from the second power source when power is not available from the first power source, and to substantially prevent current from flowing from the first power source to the second power source. The circuit also includes a voltage regulator coupled between the first power source and the second power source, adapted to regulate voltage such that a voltage from the first power source and a voltage from the second power source are approximately equal.

Peripheral device power management circuit and method for selecting between main and auxiliary power sources or from third power source

A circuit and method thereof for arbitrating between a plurality of power sources connected to a computer system peripheral device. The circuit includes a first circuit subassembly coupled to a first power source and a second power source. The first circuit subassembly conducts current from the first power source when power is not available from the second power source, and otherwise conducts current from the second power source. The circuit also includes a second circuit subassembly coupled between the first circuit subassembly and a third power source. The second circuit subassembly conducts current from the third power source when the third power source is available and otherwise conducts current from the first circuit subassembly. The second circuit subassembly comprises a first component, a second component and a third component. The first component is coupled to the third power source and the first circuit subassembly. The first component conducts current from the first circuit subassembly when power is not available from the third power source and otherwise substantially does not conduct current. The second component is coupled to the third power source and the first component. The second component conducts current from the first component when power is available from the third power source and otherwise substantially does not conduct current. The third component is coupled to the first component, the second component and the third power source. The third component conducts current from the third power source when power is available from the third power source.

Power management for a peripheral component interconnect environment with auxiliary power

A circuit and method thereof for indicating availability of a power source other than a first power source in a computer system peripheral device (such as a network adapter) connected to a plurality of power sources including. The circuit includes a circuit subassembly coupled to the first power source and a second power source. The circuit subassembly conducts current from the first power source when power is not available from the second power source and otherwise conducts current from the second power source. A first component is coupled to the circuit subassembly and conducts current when the second power source is available; otherwise, it does not conduct current. A second component is coupled to the circuit subassembly and to the first component. The second component conducts current when the first component is conducting current and otherwise does not conduct current. An output lead is coupled to the second component, and the output lead provides a signal indicating the second power source is available.

Sensing auxiliary power in various peripheral component interconnect environments

An apparatus for detecting errors in a wireless communication channel comprises a receiver which receives a data stream from the wireless communication channel, a signal strength indication circuit coupled with the receiver which indicates signal strength for a received data stream, and processing resources coupled to the signal strength indication circuit which monitors the received data signal strength to detect anomalies in the strength of the received data stream, typical of erroneous data. Also, the system includes a signal phase monitoring circuit coupled with the receiver. This circuit indicates phase of the received data stream. Processing resources coupled with the signal phase monitoring circuit, monitor the received data stream phase to detect anomalies in phase of the received data stream typical of erroneous data. In addition, the data stream will include data packets having error detection codes imbedded within the data packets. Processing resources coupled with the receiver are responsive to the error detection codes to detect errors in the data packets. Thus, an error detection system based on monitoring the amplitude, and the phase of a received signal, combined with digital CRC detection techniques provides an efficient error detection system, capable of detecting interference early in transmission, allowing more rapid recovery in retries.

Error detection in a wireless LAN environment

A receiver for NRZ data does not require a separate transmission media for the clock. Rather, a clock recovery circuit is included in the receiver capable of recovering the clock based on transitions detected in the NRZ data alone. The clock recovery circuit comprises an edge detection circuit which receives the data stream and generates edge detection signals indicating transitions in the data stream. Reference clock generation circuity generates a plurality of reference clock signals shifted in phase with respect to one another. Phase quantizing circuitry is responsive to the edge detection signals and the plurality of reference clock signals. The phase quantizing circuitry generates a quantization signal indicating one of the plurality of reference clock signals having a particular phase relationship to the edge detection signals. Clock selection circuitry, having inputs coupled to the plurality of reference clock signals and an output, is responsive to the quantization signal to select the indicated reference clock as the recovered clock signal for the data stream. The reference clock generation circuity includes a local clock input to receive a local clock, and a reference generator which is responsive to the local clock to generate a first reference wave and a second reference wave one quarter cycle out of phase relative to the first reference wave. A plurality of reference clock generators generate respective reference clock signals in response to the first and second reference waves, each of the reference clock generators generating a reference clock signal having a phase determined by relative amplitudes of the first and second reference waves.

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San Jose, CA, United States of America

Scott William Mitchell