Illumina Corporation

Illumina Cambridge Limited

Other

Scott William Bailey

James M Tsay

Robert Yang

David Louis Heiner

Alexandre Richez

John M Beierle

Sean M Ramirez

Sang Ryul Park

Kevan Samiee

Peyton Shieh

Ludovic Vincent

Wei Wei

Anmiv Prabhu

Tyler Jamison Dill

Edwin Li

Yuxiang Huang

Naiqian Zhan

Sunmin Ahn

Valerie Uzzell

Samantha K Brittelle

Kristina Munoz

Leonid Malevanchik

You-Jung Cheng

Samantha Schmitt

Jonathan Philip Davis

Joseph Page

A flow cell package includes first and second surface-modified patterned wafers and a spacer layer. The first surface-modified patterned wafer includes first depressions separated by first interstitial regions, a first functionalized molecule bound to a first silane or silane derivative in at least some of the first depressions, and a first primer grafted to the first functionalized molecule in the at least some of the first depressions. The second surface-modified patterned wafer includes second depressions separated by second interstitial regions, a second functionalized molecule bound to a second silane or silane derivative in at least some of the second depressions, and a second primer grafted to the second functionalized molecule in the at least some of the second depressions. The spacer layer bonds at least some first interstitial regions to at least some second interstitial regions, and at least partially defines respective fluidic chambers of the flow cell package.

Flow cell package and method for making the same

A composition is provided that comprises a calcium carbonate slurry. The calcium carbonate slurry comprises a plurality of calcium carbonate particles suspended in a solution, where the solution comprises a dispersant and an anionic surfactant. The concentration of the calcium carbonate particles in the calcium carbonate slurry is equal to or less than about 2.0 wt. %.

Calcium carbonate slurry

A method for planarizing a dielectric layer on a semiconductor wafer while eliminating a mask and etch step, in accordance with the present invention includes providing a semiconductor wafer having trenches formed in a trench region of a substrate, and forming a dielectric layer on the semiconductor wafer to fill the trenches whereby up features form on flat surfaces of the wafer. An edge portion of the semiconductor wafer is polished to remove a portion of the dielectric layer about the edge portions of the semiconductor wafer. The dielectric layer is polished across the entire semiconductor wafer by employing a single non-stacked polishing pad and a slurry to planarize the trench regions and the up features in a single polish step such that a mask step and etch step for reducing the up features are eliminated from the polishing process.

Planarization process to achieve improved uniformity across semiconductor wafers

Growing community of inventors

San Diego, CA, United States of America

Scott William Bailey