International Business Machines Corporation

Atmel Corporation

Cadence Design Systems, Inc.

Scott Whitney Gould

Frank Ray Keyser, Iii

Terrance John Zittritsch

Paul Steven Zuchowski

Brian A Worth

Joseph Andrew Iadanza

Thomas R Bednar

Kim P Clinton

Sebastian Theodore Ventrone

Kenneth Joseph Goodnow

Douglas Willard Stout

Allan Robert Bertolet

Eric Ernest Millham

John Maxwell Cohn

David E Lackey

Steven Paul Hartman

Timothy Shawn Reny

Alvar Antonio Dean

Paul E Dunn

Patrick M Ryan

Christine Marie Fuller

Peter Anton Habitz

Frederick Furtek

Ivan L Wemple

Jeannie H Panner

Erich C Schanzenbach

Victor Paul Seidel

Wendell Ray Larsen

Ronald Raymond Palmer

Gulson Yasar

Claude Louis Bertin

William R Tonti

Wilbur David Pricer

Gustavo Enrique Tellez

Robert J Allen

Juergen Koehl

Patrick Edward Perry

Andrew D Huber

Ralph David Kilmoyer

Michael Joseph Laramie

Sally S Botala

Frank Ray Keyser Iii

Bing Chen

Mark Kwang-Jen Hsu

Wayne Kevin Beebe

Ronald Dennis Rose

Anthony M Palagonia

David John Craft

Larry Wissel

Ciaran J Brennan

Laura R Darden

Philip S Honsinger

Richard James Evans

Kenneth Ferguson

Jose L P Neves

Gulsun Yasar

Kenneth Torino

Steven Joseph Urish

Grant L Clarke, Jr

William F Smith

Mark G Marshall

Lin Lin

John S Adams

In a first aspect, an inventive apparatus for imaging a chip on a wafer includes a combined diamond chip image and kerf image having a plurality of sloped sides. The combined diamond chip image and kerf image includes a diamond chip image comprising a plurality of chip image rows that are parallel to at least one diagonal of the diamond chip image, and includes a kerf image adjacent to the diamond chip image. The kerf image comprises at least one kerf image row that is parallel to the at least one diagonal of the diamond chip image. The apparatus further includes a blocking material extending from the combined diamond chip image and kerf image to at least a periphery of an exposure field of a stepper. In a second aspect the imaging apparatus comprises an n-sided polygon-shaped combined chip image and kerf image. Also provided are inventive methods of manufacturing chips, and wafers manufactured in accordance with the inventive methods.

Method and apparatus for manufacturing diamond shaped chips

An integrated system and method to achieve ESD robustness on an integrated circuit (IC) in a fully automated ASIC design environment is described. Electrical characteristics and electrical limits on the power network are translated to power route region constraints for each chip input/output (I/O) cell. Electrical limits on the signal network are translated into signal route region constraints for each chip I/O cell. These constraints are passed on to an I/O floorplanner (automatic placer of I/O cells) that analyzes trade-offs between these constraints. For I/O cells that can not be placed to satisfy both power and signal region constraints, the I/O floorplanner utilizes the knowledge of alternative power distribution structures to group I/Os and create local power grid structures that have the effect of relaxing the power region constraints. Instructions for creating these local power grid structures are passed on to the automatic power routing tool.

Electrostatic discharge failure avoidance through interaction between floorplanning and power routing

A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levels 1 to N&#x2212;1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.

Method and apparatus for performing power routing on a voltage island within an integrated circuit chip

An integrated circuit. The integrated circuit includes a parent terrain; and a hierarchical order of nested voltage islands within the parent terrain, each higher-order voltage island nested within a lower-order voltage island, each nested voltage island having the same hierarchical structure.

Nested voltage island architecture

Macro design techniques are disclosed for facilitating subsequent stage wiring across the macro. Whitespace areas within the macro are rearranged to accommodate the wiring. The rearrangement may take the form of physical rearrangement of the whitespace areas into routing tracks extending from one side of the macro to another; shielding using, for example, macro power bussing and/or macro wiring; routing power busses to the rearranged whitespace; and/or inserting active circuits with pins accessible to the wiring. In a preferred embodiment, active circuits are placed into rearranged macro whitespace during the design of subsequent stages. The rearrangement of the whitespace facilitates the wiring across the macro so that slew rate and path delay requirements of the subsequent stage wiring can be maintained, without excessive buffering or rerouting of wiring.

Macro design techniques to accommodate chip level wiring and circuit placement across the macro

A method and structure for designing an integrated circuit chip supplies a chip design and partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands. The invention outputs a voltage island specification list comprising power and timing information of each voltage island; and automatically, and without user intervention, synthesizes power supply networks for the voltage islands.

Voltage island chip implementation

A method for performing power routing on a voltage island within an integrated circuit chip is disclosed. A first power grid is generated for a voltage island on metal levelsto N&#x2212;1. Then, a second power grid is generated on metal levels N and above. A bounding region of the second robust power grid is determined. Finally, the shortest distance connections from a set of power sources is routed to the second power grid.

A method and system for analyzing power distribution in an integrated circuit chip includes dividing a clock cycle of the integrated circuit chip into a plurality of time periods, dividing the integrated circuit chip into a plurality of cells, performing a static timing analysis for the plurality of cells to obtain current waveform data for each cell and each time period, and performing a power distribution analysis using the current waveform data.

System and method for analyzing power distribution using static timing analysis

An integrated circuit, method and system providing finer granularity dynamic voltage control without performance loss. The invention provides a means for dynamically changing a voltage level of at least one stage on a critical path for a particular cycle. In this way, optimum voltages can be provided to the stages for the given expectation.

Power reduction by stage in integrated circuit

A way of dynamically modifying error recovery on a communications controller to operate at the lowest power mode allowed by current error rate conditions. When operating conditions are good and a small number of errors are detected, a low power error detection/correction mode is entered saving battery life. The low power error correction mechanism runs at a slower frequency and lower power than the high power mechanism and maintains the same data rate for the controller, thus saving power. Selecting the controller error (power) mode may be externally, such as by a person using a control dial on a cellular telephone when the voice data gets too noisy. Alternatively, the selection can be automatic, a critical error level detector internally making the selection.

Low-power critical error rate communications controller

A method and structure for designing an integrated circuit chip is disclosed. The method supplies a chip design, partitions elements of the chip design according to similarities in voltage requirements and timing of power states of the elements to create voltage islands, creates a floorplan of the voltage islands, assesses the floorplan, repeats the partitioning and the creating of the floorplan depending upon a result of the assessing process, and outputs a voltage island specification list.

Voltage island design planning

A method and apparatus for buffering a signal in a voltage island that is in standby or sleep mode. The apparatus uses a buffer(s) that are powered from a global power supply voltage that is always powered, and such buffer(s) are placed within the sleeping island itself. The sleeping island can be at the same or different voltage from the global voltage.

Global voltage buffer for voltage islands

Growing community of inventors

South Burlington, VT, United States of America

Scott Whitney Gould