Advanced Micro Devices Corporation

Scott Waldron

John C Peck, Jr

Stephen T Novak

Sridhar P Subramanian

Ranjit Joseph Rozario

Ravikrishna Cherukuri

Jacques Ah Wong

Mark William Knecht

Jacques Ah Miow Wong

A system includes a main memory device which stores information for translating a virtual address into a physical address in response to one of a plurality of processing devices. A memory control/interface device is coupled to the main memory device. The memory control/interface device, which may access the information stored in the main memory device, has a separate translation look-aside buffer for each processing device. Each translation look-aside buffer can buffer the information for use in translating in response to the respective processing device.

Distributed translation look-aside buffers for graphics address remapping table

A system and method are provided for optimizing the translation of virtual addresses into physical addresses for a graphics address remapping table (GART). In the system and method, a translation look-aside buffer cache has a plurality of translation look-aside buffer entries. Each translation look-aside buffer entry is operable to buffer information which may be accessed for use in translating a virtual address into a physical address. A least recently used pointer circuit is operable to point to a translation look-aside buffer entry buffering information least recently used in the translation look-aside buffer cache. During operation, updates to the least recently used pointer circuit may be pipelined with corresponding accesses to the translation look-aside buffer cache.

Optimizing the translation of virtual addresses into physical addresses using a pipeline implementation for least recently used pointer

A memory controller for a computer memory which decodes memory requests into individual primitive memory operations which are then queued into separate operation queues. The operation queues independently issue their queued primitive memory operations to the memory in order to initiate the memory request. The operation queues monitor and adhere to timing and ordering dependencies between the primitive memory operations that are queued and those that have already been transmitted to the memory. Once a primitive memory operation is transmitted to the memory, it is dequeued from its respective operation queue. A control queue monitors the progress of the primitive memory operations transmitted to the memory, completes the initiated memory request and provides timing and ordering dependency data to the operation queues.

Queue based memory controller

A system (,) for automatically ordering a request for access to a system memory (,) is disclosed. The system (,) includes a re-ordering buffer (,) having a data input (,) and a data output (,) and an input request position identifier (,) associated with the re-ordering buffer (,). The input request position identifier (,) indicates a position of the data input (,) in the re-ordering buffer (,) for the new request based on a status of the request. A method (,) of ordering a request for access to a system memory (,) in a buffer (,) is also disclosed and includes initiating a request (,) for access to the system memory (,), wherein the request contains a status indicating a priority of the request. The status of the request is evaluated (,) to determine whether the request is a high priority request or a low priority request and a location for inputting the access request into the buffer (,) is identified (,) in response to the evaluation. One or more previously requested access requests are then shifted (,) within the buffer if necessary to make room for the access request at the identified location and the new access request is inserted into the buffer at the identified location (,).

Arbitrating FIFO implementation which positions input request in a buffer according to its status

A method and apparatus for managing interrupt requests from devices on a subordinate bus is disclosed. An interrupt request storage area is provided on the bridge device to allow the bridge device to log and track interrupt requests. Once an interrupt request from an interrupting device is logged, all previous transactions from the interrupting device is allowed to complete while no further transactions from the interrupting device is allowed. All other devices operates normally during this time. Once the interrupt request is serviced, the interrupting device is allowed to resume normal operation. By providing a storage area to store the interrupt requests from devices on a subordinate bus, the unprocessed transactions in the bridge device and transactions from all other devices can be processed in an orderly manner.

Interrupt gating method for PCI bridges

An improved bus bridge in a computer system for connecting a first data bus and a second data bus, said bus bridge having means for connecting said first and second buses, means for receiving an address representing a transaction on said first bus, means for decoding said address, means for claiming the transaction on said first bus corresponding to said address, and means for passing said transaction to said second bus, wherein the improvement comprises: (a) means for determining if said address decodes into one of a plurality of address ranges programmed in said bridge device; (b) means for determining a timing speed for the transaction corresponding to said address in accordance with the address range for said address; and (d) means for asserting a signal for claiming the transaction at said determined timing speed.

Bus bridge that provides selection of optimum timing speed for transactions

A memory controller for a dynamic random access memory having counters for each chip select in the memory. The counters are incremented at a fixed interval. Programmable threshold values are provided which, when compared with the counters, indicate to the memory controller when a refresh should be opportunistically attempted and when a refresh is urgently required. The memory controller then either attempts to find an idle cycle to send the opportunistic refresh or blocks memory accesses to create a window for an urgently needed refresh. Once a refresh is sent to the memory, the appropriate counter is decremented accordingly.

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Belmont, CA, United States of America

Scott Waldron