Advanced Micro Devices Corporation

Xilinx, Inc.

Scott Thomas Bingham

William Louie Walker

Marius Evers

Krishnan V Ramani

John Kalamatianos

David S Christie

Paul J Moyer

Richard Martin Born

Eric Christopher Morton

John M King

Michael Estlick

William Evan Jones, Iii

Erik D Swanson

Kai Troester

Pongstorn Maidee

Thomas Kunjan

Susumu Mashimo

Manivannan Bhoopathy

Rajesh Kumar Arunachalam

Robert Weidner

Hon-Hin Wong

Richard Carlson

The disclosed device includes a processor and an interconnect connecting the processor to a memory. The interconnect includes an interconnect agent that can forward memory requests from the processor to the memory and receive requested data returned by the memory. The requested data can include information for a next memory request such that the interconnect agent can send, to the memory, a speculative memory request using information for the next memory request that was received in response to the memory request. Various other methods, systems, and computer-readable media are also disclosed.

Remote acceleration for data dependent address calculation

The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

Encoded data dependency matrix for power efficiency scheduling

A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.

Masked multi-lane instruction memory fault handling using fast and slow execution paths

A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

Speculative instruction wakeup to tolerate draining delay of memory ordering violation check buffers

A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

Processor with accelerated lock instruction operation

A method and apparatus for performing a bus lock and a translation lookaside buffer invalidate transaction includes receiving, by a lock master, a lock request from a first processor in a system. The lock master sends a quiesce request to all processors in the system, and upon receipt of the quiesce request from the lock master, all processors cease issuing any new transactions and issue a quiesce granted transaction. Upon receipt of the quiesce granted transactions from all processors, the lock master issues a lock granted message that includes an identifier of the first processor. The first processor performs an atomic transaction sequence and sends a first lock release message to the lock master upon completion of the atomic transaction sequence. The lock master sends a second lock release message to all processors upon receiving the first lock release message from the first processor.

Method and apparatus for performing a bus lock and translation lookaside buffer invalidation

Growing community of inventors

Santa Clara, CA, United States of America

Scott Thomas Bingham