Tram, Inc.

T-ram Semiconductor, Inc.

Micron Technology Incorporated

Other

Scott T Robins

Andrew Edward Horch

Farid Nemati

Hyun-Jin Cho

Rajesh N Gupta

Kevin J Yang

Zachary K Lee

James D Plummer

Tapan Samaddar

Badredin Fatemizadeh

Marc Laurent Tarabbia

Srinivasa Banna

Rajesh Gupta

Some embodiments include gated bipolar junction transistors. The transistors may include a base region between a collector region and an emitter region; with a B-C junction being at an interface of the base region and the collector region, and with a B-E junction being at an interface of the base region and the emitter region. The transistors may include material having a bandgap of at least 1.2 eV within one or more of the base, emitter and collector regions. The gated transistors may include a gate along the base region and spaced from the base region by dielectric material, with the gate not overlapping either the B-C junction or the B-E junction. Some embodiments include memory arrays containing gated bipolar junction transistors. Some embodiments include methods of forming gated bipolar junction transistors.

Gated bipolar junction transistors, memory arrays, and methods of forming gated bipolar junction transistors

Some embodiments include thyristors having first and second electrode regions, first and second base regions, and material having a bandgap of at least 1.2 eV in at least one of the regions. The first base region is between the first electrode region and the second base region, and the second base region is between the second electrode region and the first base region. The first base region interfaces with the first electrode region at a first junction, and interfaces with the second base region at a second junction. The second base region interfaces with the second electrode region at a third junction. A gate is along the first base region, and in some embodiments does not overlap either of the first and second junctions. Some embodiments include methods of programming thyristors, and some embodiments include methods of forming thyristors.

Thyristors, methods of programming thyristors, and methods of forming thyristors

Thyristors

Gated bipolar junction transistors

A thyristor based semiconductor device includes a thyristor having cathode, P-base, N-base and anode regions disposed in electrical series relationship. The N-base region for the thyristor has a cross-section that defines an inverted 'T' shape, wherein a buried well in semiconductor material forms is operable as a part of the N-base. The stem to the inverted 'T' shape extends from the upper surface of the semiconductor material to the buried well. The P-base region for the thyristor extends laterally outward from a side of the stem that is opposite the anode region of the thyristor, and is further bounded between the buried well and a surface of the semiconductor material. A thinned portion for the N-base is defined between the cathode region of the thyristor and the buried well, and may include supplemental dopant of concentration greater than that for some other portion of the N-base.

Thyristor semiconductor memory and method of manufacture

Gettering contaminants for formation of integrated circuits on a semiconductor-on-insulator structure is described. A semiconductor-on-insulator structure is configured to attract contaminants. Contaminant attractor regions are formed using ion implantation into a semiconductor layer of the semiconductor-on-insulator structure. The semiconductor layer is located above a buried insulator layer of the semiconductor-on-insulator structure. The contaminant attractor regions are spaced away from active regions. Tiles are located on an upper surface of the buried insulator layer. The contaminant attractor regions are formed adjacent to, in close proximity to, or in the tiles. At least one dielectric layer laterally adjacent to the tiles and is disposed on the upper surface of the buried insulator layer. The at least one dielectric layer at least inhibits lateral migration of contaminants to the active regions.

Gettering contaminants for integrated circuits formed on a silicon-on-insulator structure

A semiconductor device having a thyristor-based device and a pass device exhibits characteristics that may include, for example, resistance to short channel effects that occur when conventional MOSFET devices are scaled smaller in connection with advancing technology. According to an example embodiment of the present invention, the semiconductor device includes a pass device having a channel in a fin portion over a semiconductor substrate, and a thyristor device coupled to the pass device. The fin has a top portion and a side portion and extends over the semiconductor substrate. The pass device includes source/drain regions separated by the channel and a gate facing and capacitively coupled to the side portion of the fin that includes the channel. The thyristor device includes anode and cathode end portions, each end portion having base and emitter regions, where one of the emitter regions is coupled to one of the source/drain regions of the pass device. The gate of the pass device is further adapted to switch the pass device between a blocking state and a conducting state via the capacitive coupling and form a conductive path between the source/drain regions. A control port is capacitively coupled to the base region of the end portion of the thyristor that is coupled to the source/drain region of the pass gate and is adapted to facilitate switching of the thyristor between blocking and conducting states.

Fin thyristor-based semiconductor device

A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. The memory cell contains a thyristor body and a gate. The thyristor body has two end region and two base regions, and it is disposed on top of a well. The memory cell is positioned between two isolation regions, and the isolation regions are extended below the well. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

Thyristor based memory cell

A new memory cell contains only a single thyristor without the need to include an access transistor. A memory array containing these memory cells can be fabricated on bulk silicon wafer. Each memory cell is separated from other memory cells by shallow trench isolation regions. The memory cell comprises a thyristor body and a gate. The thyristor body has two end region and two base regions. The gate is positioned over and insulated from at least a portion of one base region and offset from another base region. A first end region is connected to one of a word line, a bit line and a third line. A second end region is connected to another of the word line, bit line, and third line. The gate is connected to the remaining of the word line, bit line and third line.

A semiconductor device may comprise a partially-depleted SOI MOSFET having a floating body region disposed between a source and drain. The floating body region may be driven to receive injected carriers for adjusting its potential during operation of the MOSFET. In a particular case, the MOSFET may comprise another region of semiconductor material in contiguous relationship with a drain/source region of the MOSFET and on a side thereof opposite to the body region. This additional region may be formed with a conductivity of type opposite the drain/source, and may establish an effective bipolar device per the body, the drain/source and the additional region. The geometries and doping thereof may be designed to establish a transport gain of magnitude sufficient to assist the injection of carriers into the floating body region, yet small enough to guard against inter-latching with the MOSFET.

High ion/Ioff SOI MOSFET using body voltage control

In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Thyristor device with carbon lifetime adjustment implant and its method of fabrication

An integrated circuit having memory, including thyristor-based memory cells, is described, where each of the thyristor-based memory cells includes a thyristor-based storage element and an access transistor. Where the thyristor-based storage element includes an anode region and a cathode region, a pair of the thyristor-based memory cells are commonly coupled via a bitline associated with the access transistor or via a reference voltage line coupled to the anode region. Bitline or anode regions are separated from one another by an isolation region. In another configuration, a bitline region has a locally implant-damaged region to inhibit charge transfer between the pair. In yet another configuration, a storage node contact or contacts respectively can extend over or are coupled to a storage node line extending over an isolation region. In this latter configuration, a source/drain region and the cathode region are separated from one another by an isolation region.

Reducing effects of parasitic transistors in thyristor-based memory using an isolation or damage region

A method of fabricating a thyristor-based memory may include forming different opposite conductivity-type regions in silicon for defining a thyristor and an access device in series relationship. An activation anneal may activate dopants previously implanted for the different regions. A damaging implant of germanium or xenon or argon may be directed into select regions of the silicon including at least one p-n junction region for the access device and the thyristor. A re-crystallization anneal may then be performed to re-crystallize at least some of the damaged lattice structure resulting from the damaging implant. The re-crystallization anneal may use a temperature less than that of the previous activation anneal.

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San Jose, CA, United States of America

Scott T Robins