Compaq Computer Corporation, Inc.

Other

Scott T McFarland

Bassam N Elkhoury

Miguel A Perez

In a method and system for use in connection with performing a processor-to-bus cycle in a multi-processor computer system, the processor-to-bus cycle is interrupted before completion and an operation to save data in memory is performed. Thereafter, the interrupted processor-to-bus cycle is resumed.

Memory coherency in a processor-to-bus cycle in a multi-processor system

In a method and system for performing a memory access cycle from a first processor to a memory address in a multi-processor system, the memory access cycle is initiated, and, prior to completion of the memory access cycle, a snoop routine is initiated with respect to the memory address. The memory access cycle is continued without awaiting responses from another one of the processors if a second one of the processors provides a signal which indicates that immediate completion of the memory access cycle will not disturb the integrity of data stored in the system.

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Kingwood, TX, United States of America

Scott T McFarland