Cisco Technology, Inc.

Scott Smith

Christopher J Kappler

Gregory S Goss

Robert C Olsen

William Robert Lee

Andrew T Hebb

Robert Jeter

Trevor Gamer

Achot Matevossian

Gegory Goss

Techniques for processing each of multiple threads that share a core processor include receiving an intra-thread register address from the core processor. This address contains C bits for accessing each of 2registers for each thread. A thread ID is received from a thread scheduler external to the core processor. The Thread ID contains T bits for indicating a particular thread for up to 2threads. A particular register is accessed in a register bank that has 2registers using an inter-thread address that includes both the intra-thread register address and the thread ID. The particular register holds contents for the intra-thread register address for a thread having the thread ID. Consequently, register contents of all registers of all threads reside in the register bank. Thread switching is accomplished rapidly by simply accessing different slices in the register bank, without swapping contents between a set of registers and memory.

Techniques for hardware-assisted multi-threaded processing

Queues are scheduled for outputting data using a hierarchical tree. Each level of the hierarchical tree includes multiple entries for storing status information associated with the queues. For example, a given entry of the tree stores multi-parameter status information associated with a corresponding queue to be serviced. To determine which of the queues is next in line for servicing, a logic circuit compares the multi-parameter status information stored in two or more entries of the tree. The next scheduled queue or highest priority queue in the tree is then serviced by outputting at least some of its data.

Methods and apparatus for scheduling tasks

Conventional schedulers employ designs allocating specific processor and memory resources, such as memory for configuration data, state data, and scheduling engine processor resources for specific aspects of the scheduler, such as layers of the scheduling hierarchy, each of which consumes dedicated processor and memory resources. A generic, iterative scheduling engine, applicable to an arbitrary scheduling hierarchy structure having a variable number of hierarchy layers, receives a scheduling hierarchy structure having a predetermined number of layers, and allocates scheduling resources such as instructions and memory, according to scheduling logic, in response to design constraints and processing considerations. The resulting scheduling logic processes the scheduling hierarchy in iterative manner which allocates the available resources among the layers of the hierarchy, such that the scheduler achieves throughput requirements corresponding to enqueue and dequeue events with consideration to the number of layers in the scheduling hierarchy and the corresponding granularity of queuing.

Iterative architecture for hierarchical scheduling

One or more queues store data information such as packets or data flows for later transmission to downstream communication devices. A real-time clock tracks current time and an advancement of a moving time reference, which is displaced with respect to the current time of the clock by an offset value. Thus, as current time advances, the moving time reference also advances in time. Upon servicing a queue, a time stamp associated with the serviced queue is also advanced in time. To monitor a rate of outputting data from the one or more queues, a processor device at least occasionally adjusts the offset value so that the moving time reference and values of the time stamps advance in relation to each other. Consequently, by tracking a relative time difference between current time of the real-time clock and a relative advancement of time stamps, a rate of outputting data information from the queue is monitored over time.

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Mansfield, MA, United States of America

Scott Smith