Texas Instruments Corporation

Other

Advanced Technology Materials, Inc.

Raytheon Company

Agilent Technologies, Inc.

California Institute of Technology

Agilent Technologies Texas Instruments Incorporated

Scott Robert Summerfelt

Howard R Beratan

Theodore Sidney Moise

Hugh Pryor McAdams

Stephen Roy Gilbert

Luigi Colombo

Francis Gabriel Celii

Sanjeev Aggarwal

Kezhakkedath Ramunni Udayakumar

Bruce E Gnade

Benjamin Stassen Cook

Steven Craig Bartling

Guoqiang Xing

Ted S Moise

John Anthony Rodriguez

Lindsey H Hall

Mark R Visokay

James F Belcher

Yasushiro Nishioka

K R Udayakumar

Kyung-ho Park

Peter S Kirlin

John Paul Campbell

Monte A Douglas

Bichoy Bahr

Michael Patrick Clinton

Bernard M Kulwicki

Justin F Gaynor

Darius Lammont Crenshaw

Tomoyuki Sakoda

Thomas Dyer Bonifield

Chih-Chen Cho

Glen D Wilk

Manoj K Jain

Wei-Yan Shih

Rajni J Aggarwal

Paul C McIntyre

John Mark Anthony

Chiu Chi

Sreenivasan Kalyani Koduri

Laura Wills Mirkarimi

Peter Smeys

Jules D Levine

Robert M Wallace

Shawming Ma

Rajesh B Khamankar

Robert Kraft

Terry Lee Sculley

Kaichien Tsai

Shaoping Tang

Sreeram Subramanyam Nasum

Alok Kumar Lohia

Hasibur Rahman

Steve Kummerl

Yasutoshi Okuno

Scott Kelly Montgomery

John Britton Robbins

Ralf Jakobskrueger Muenster

Seung Bae Lee

Haowen Bu

Byron Lovell Williams

Peter C Van Buskirk

Sudhanshu Khanna

Wei-Yung Hsu

Adam Joseph Fruehling

Yaw S Obeng

Charles M Hanson

Scott David Johnson

Kelly Jay Taylor

Daniel Lee Revier

Robert A Owen

Jun Amano

Hassan Omar Ali

Ernst Georg Muellner

Keith Ryan Green

Robert Yung-Hsi Tsu

Asad Mahmood Haider

Richard Allen Bailey

Jarrod Eliason

Steven N Frank

Nicholas Stephen Dellas

Gregory Boyd Shinn

Gregory Allen North

Michael Zwerg

Juergen Luebbe

James W Grace

Poornika Fernandes

Sebastian Meier

Michael W Russell

Trace Quentin Hurd

Kemal Tamer San

Borna J Obradovic

Neng Jiang

Daniel J Vestyck

Stephen Arlon Meisner

Eden M Zielinski

Katsushi Boku

Juergen T Rickes

Mark A Kressley

Thomas Warren Lassiter

A method includes depositing a first epitaxial layer of an aluminum gallium nitride (AlGaN) material onto a preliminary substrate and polishing the first layer's surface. Ions are implanted beneath the surface, which is bonded to a seed insulating substrate. Annealing is performed, resulting in second epitaxial layer on preliminary substrate and third epitaxial layer on seed insulating substrate. Third layer's surface is polished to obtain a seed wafer. In some implementations, a fourth epitaxial layer of a second AlGaN material is deposited onto surface of third layer. Fourth layer's surface is polished, and ions are implanted beneath the surface, which is bonded to a product insulating substrate. Annealing is performed, resulting in fifth epitaxial layer on seed insulating substrate and sixth epitaxial layer on product insulating substrate. The sixth layer can be used to obtain an AlGaN product, and the fifth layer can be reused to fabricate additional AlGaN products.

Technique for GaN epitaxy on insulating substrates

In some examples, a package comprises a semiconductor die having a first surface and a second surface opposing the first surface, the semiconductor die including circuitry formed in the first surface. The package includes an acoustic waveguide in the semiconductor die, the acoustic waveguide including an array of capacitors. The array of capacitors includes a transducer portion and a diffraction grating portion. The transducer portion is configured to convert signals between electrical signals and acoustic waves, and the diffraction grating portion is configured to direct the acoustic waves toward and receive the acoustic waves from the second surface.

Acoustic waveguide with diffraction grating

In described examples of an integrated circuit (IC) there is a substrate of semiconductor material having a first region with a first transistor formed therein and a second region with a second transistor formed therein. An isolation trench extends through the substrate and separates the first region of the substrate from the second region of the substrate. An interconnect region having layers of dielectric is disposed on a top surface of the substrate. A dielectric polymer is disposed in the isolation trench and in a layer over the backside surface of the substrate. An edge of the polymer layer is separated from the perimeter edge of the substrate by a space.

Through wafer trench isolation between transistors in an integrated circuit

A micro-electromechanical system (MEMS) device includes a moveable element within a cavity. The MEMS device also includes a first layer over the cavity, the first layer having a first hole and a second hole. The first hole has a first diameter. The second hole has a second diameter. The second diameter is larger than the first diameter, and the second hole is farther from the moveable element than the first hole. The first hole is sealed with a first dielectric material. The second hole is sealed with a second dielectric material. The cavity filled with a gas at a pressure of at least approximately 10 torr.

MEMS encapsulation employing lower pressure and higher pressure deposition processes

A method includes measuring a temperature of a semiconductor die, in which the semiconductor die includes a piezoelectric device, a pyroelectric device, and a memory. The method further includes receiving a first signal from the pyroelectric device, and based on the first signal, determining a parameter to be combined with a second signal from the piezoelectric device. The method further includes storing the parameter and the measured temperature into the memory.

Aging compensation of a ferroelectric piezoelectric shock sensor

In some examples, an electronic device comprises a first component having a surface, a second component having a surface, and a bond layer positioned between the surfaces of the first and second components to couple the first and second components to each other. The bond layer includes a set of metallic nanowires and a dielectric portion. The dielectric portion comprises a polymer matrix and dielectric nanoparticles.

Dielectric and metallic nanowire bond layers

An integrated circuit (IC) including a semiconductor surface layer of a substrate including functional circuitry having circuit elements formed in the semiconductor surface layer configured together with a Metal-Insulator-Metal capacitor (MIM) capacitor on the semiconductor surface layer for realizing at least one circuit function. The MIM capacitor includes a multilevel bottom capacitor plate having an upper top surface, a lower top surface, and sidewall surfaces that connect the upper and lower top surfaces (e.g., a bottom plate layer on a three-dimensional (3D) layer or the bottom capacitor plate being a 3D bottom capacitor plate). At least one capacitor dielectric layer is on the bottom capacitor plate. A top capacitor plate is on the capacitor dielectric layer, and there are contacts through a pre-metal dielectric layer to contact the top capacitor plate and the bottom capacitor plate.

IC with 3D metal-insulator-metal capacitor

For sensing pH of a fluid, a heating apparatus of a semiconductor die controls a temperature of the fluid to a first temperature. A first voltage of a gate of a floating gate transistor of the semiconductor die is measured while the temperature of the fluid is at the first temperature. Also, the heating apparatus controls the temperature of the fluid to a second temperature that is different than the first temperature. A second voltage of the gate is measured while the temperature of the fluid is at the second temperature. The pH of the fluid is determined based on the first and second voltages, the first temperature and the second temperature.

PH sensor

Curing of a passivation layer applied to the surface of a ferroelectric integrated circuit so as to enhance the polarization characteristics of the ferroelectric structures. A passivation layer, such as a polyimide, is applied to the surface of the ferroelectric integrated circuit after fabrication of the active devices. The passivation layer is cured by exposure to a high temperature, below the Curie temperature of the ferroelectric material, for a short duration such as on the order of ten minutes. Variable frequency microwave energy may be used to effect such curing. The cured passivation layer attains a tensile stress state, and as a result imparts a compressive stress upon the underlying ferroelectric material. Polarization may be further enhanced by polarizing the ferroelectric material prior to the cure process.

Low-temperature passivation of ferroelectric integrated circuits for enhanced polarization performance

A microelectronic device is formed by dispensing discrete amounts of a mixture of photoresist resin and solvents from droplet-on-demand sites onto a wafer to form a first photoresist sublayer, while the wafer is at a first temperature which allows the photoresist resin to attain less than 10 percent thickness non-uniformity. The wafer moves under the droplet-on-demand sites in a first direction to form the first photoresist sublayer. A portion of the solvents in the first photoresist sublayer is removed. A second photoresist sublayer is formed on the first photoresist sublayer using the droplet-on-demand sites while the wafer is at a second temperature to attain less than 10 percent thickness non-uniformity in the combined first and second photoresist sublayers. The wafer moves under the droplet-on-demand sites in a second direction for the second photoresist sublayer, opposite from the first direction.

Methods and apparatus for digital material deposition onto semiconductor wafers

An integrated force sensing element includes a piezoelectric sensor formed in an integrated circuit (IC) chip and a strain gauge at least partially overlying the piezoelectric sensor, where the piezoelectric sensor is able to flex. A human-machine interface using the integrated force sensing element is also disclosed and may include a conditioning circuit, temperature gauge, FRAM and a processor core.

Piezoelectric sensor apparatus

In described examples of a CMOS IC, an ultrasonic transducer having terminals is formed on a substrate of the IC. CMOS circuitry having ultrasonic signal terminals is formed on the substrate. At least one metal interconnect layer overlies the ultrasonic transducer and the CMOS circuitry. The at least one metal interconnect layer connects the CMOS circuitry ultrasonic signal terminals to the terminals of the ultrasonic transducer.

High frequency CMOS ultrasonic transducer

In described examples an integrated circuit (IC) has multiple layers of dielectric material overlying at least a portion of a surface of a substrate. A trench is etched through the layers of dielectric material to expose a portion the substrate to form a trench floor, the trench being surrounded by a trench wall formed by the layers of dielectric material. A metal perimeter band surrounds the trench adjacent the trench wall, the perimeter band being embedded in one of the layers of the dielectric material.

Optical sensor with trench etched through dielectric over silicon

A method includes measuring a first signal from a set of pyroelectric devices at a first temperature and measuring a second signal from a set of piezoelectric devices at a first acceleration. The method also includes measuring a third signal from the set of pyroelectric devices at a second temperature and measuring a fourth signal from the set of piezoelectric devices at a second acceleration. The method further includes adjusting a piezoelectric calibration using the first, second, third, and fourth signals.

An oscillator assembly includes a scribe seal, an oscillator circuit, and a calibration circuit. The oscillator circuit includes an output. The calibration circuit is coupled to the oscillator circuit. The calibration circuit includes a reference frequency terminal, a conductor coupled to the reference frequency terminal, and an oscillator input terminal. The conductor extends to an edge of the oscillator circuit assembly and penetrates the scribe seal. The oscillator input terminal is coupled to the output of the oscillator circuit.

Oscillator self-calibration

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Garland, TX, United States of America

Scott Robert Summerfelt