Micron Technology Incorporated

Scott Richard Cyr

Timothy Mowry Hollis

Matthew B Leslie

Yoshihisa Fukushima

Wataru Tsukada

Masayuki Honda

Matthew Alan Prather

Scott Eugene Smith

Ross S Dando

Eric J Stave

Baekkyu Choi

Dirgha Khatri

William Anthony Lendvay

Yogesh Sharma

Stephen F Moxham

Elancheren Durai

Quincy R Holton

Boe L Holbrook

Memory devices, systems including memory devices, and methods of operating memory devices are described, in which clock trees can be separately optimized to provide a coarse alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal), and/or in which individual memory devices can be isolated for fine-tuning of device-specific alignment between a clock signal and a command/address signal (and/or a chip select signal or other control signal). Moreover, individual memory devices can be isolated for fine-tuning of device-specific equalization of a command/address signal (and/or a chip select signal or other control signal).

Methods for tuning command/address bus timing and memory devices and memory systems using the same

Apparatuses, such as semiconductor device packages, may include, for example, a device substrate including a semiconductor material and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on, and electrically connected to, the package substrate. Each ball of the ball grid array positioned and configured to carry a clock signal or a strobe signal may be located in a central column of the ball grid array.

Apparatuses and systems having ball grid arrays and associated microelectronic devices and device packages

Methods, systems, and devices for pin mapping for memory devices are described. An apparatus may include a memory array, a plurality of pins, a selector, and a mapping component. The memory array may include a plurality of data lines coupled with a plurality of memory cells. The mapping component may be configured to map a set of data lines to a first set of pins when the selector reflects a first state and to a second set of pins when the selector reflects a second state. The first and second set of pins may have a same quantity of pins. The second set of pins may include pins that are otherwise unused in the second state. The mapping component may be configured to selectively couple unused pins to a fixed potential.

Pin mapping for memory devices

A semiconductor module includes a module substrate, a line pattern provided to the module substrate, first and second semiconductor chips on the module substrate and coupled to the line pattern, and a termination resister on the module substrate and coupled to the line pattern, the termination resistor being located between the first and second semiconductor chips.

Semiconductor memory device including output buffer

Semiconductor device assemblies with semiconductor device packages configured to operate in mirror mode are disclosed herein. In one embodiment a semiconductor device assembly includes a first semiconductor device package attached to a front side of a support substrate, and a second semiconductor device package attached to a back side of the support substrate. The first device package includes a plurality of first package contacts having a first arrangement of corresponding pin assignments, and the second device package includes a plurality of second package contacts and a switch circuit operably coupled to the second package contacts. The switch circuit is configured to receive a switch signal via the support substrate, and to assign the second package contacts to either the first arrangement of corresponding pin assignments or a second arrangement of corresponding pin assignments based on the switch signal.

Semiconductor device package with mirror mode

In one aspect, the invention encompasses a system for electronic identification of a plurality of units. The system comprises transponders which are connected with respective individual units, and which comprise antennas. The system further comprises an interrogator configured to read the transponders. The interrogator includes an interrogator antenna. At least one of the interrogator antenna or the transponder antennas comprise a coil of conductive material which has a first planar portion within a first plane and a second planar portion within a second plane, with the first and second planes intersecting. In another aspect, the invention comprises a method for electronic identification of a plurality of passing animal bodies, wherein the individual animal bodies have respective transponders associated therewith. An interrogator having an antenna associated therewith is provided. The antenna is proximate a housing with a periphery having a shape comprising a recessed central region and a projecting peripheral region extending from the central region. Animal bodies are passed by the housing, and at least some of the passing animal bodies are purposefully bumped against the projecting peripheral region. The bumping into the projecting peripheral region changes an orientation of transponders associated with the individual passing animal bodies relative to the antenna.

Apparatuses for electronic identification of a plurality of passing

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Eagle, ID, United States of America

Scott Richard Cyr