Intel Corporation

Other

Scott R Janus

Prasoonkumar Surti

Abhishek R Appu

Joydeep Ray

Altug Koker

Vasanth Ranganathan

Varghese George

Lakshminarayanan Striramassarma

Elmoustapha Ould-Ahmed-Vall

Subramaniam M Maiyuran

Brent E Insko

Mike MacPherson

Arthur Hunter, Jr

Jill MacDonald Boyce

Aravindh V Anantaraman

Valentin Andrei

Kamal Sinha

Changliang Wang

Sungye Kim

Karthik Vaidyanathan

Carsten Benthin

Philip R Laws

Vikranth Vemulapalli

Ben J Ashbaugh

Nicolas C Galoppo Von Borries

Narayan Biswal

Selvakumar Panneer

Hugues Labbe

Balaji Vembu

Pattabhiraman K

Nilesh V Shah

Sanjeev S Jahagirdar

Murali Ramadoss

Adam T Lake

Carl S Marshall

Deepak Shashidhar Vembar

Stanley J Baran

Karthik Veeramani

Gokcen Cilingir

Xinmin Tian

Barnan Das

Jonathan D Pearce

Uday R Savagaonkar

Michael Apodaca

Jason Daniel Tanner

Richmond Hicks

Gabor Liktor

Nausheen Ansari

Sang-Hee Lee

Jason Martin

Jong Dae Oh

Ya-Ti Peng

Archie Sharma

Arthur Jeremy Runyan

Keith W Rowe

Robert J Johnston

Nikos Kaburlasos

Kai Xiao

Atsuo Kuwahara

Vallabhajosyula S Somayazulu

James M Holland

Sven Woop

Sang-hee Lee

Ashutosh Garg

Mayuresh M Varerkar

Nilesh K Jain

Alexey Supikov

Sherine Abdelhak

David M Durham

Glen J Anderson

Siddhartha Chhabra

Prashant Dewan

Ankur N Shah

Lidong Xu

David M Puffer

James A Valerio

Daniel Nemiroff

Ravi L Sahita

Yi-Jen Chiu

Hong Jiang

Guei-Yuan Lueh

David Wyatt

Carlos V Rozas

Anbang Yao

Francis X Mckeen

Vincent R Scarlata

Ravishankar Iyer

Geoffrey S Strongin

Michael A Smith

Eric C Samson

Aditya Navale

Karanvir S Grewal

Ximin Zhang

Qian Xu

Niranjan L Cooray

Michael A Goldsmith

Josh B Mastronarde

Val Gene Cook

Radhakrishnan Venkataraman

Yunbiao Lin

Example methods, apparatus, systems and articles of manufacture (e.g., physical storage media) to implement multi-plane image (MPI) compression are disclosed. Example apparatus disclosed herein include an interface to access an input multiplane image stack corresponding to a source camera viewpoint, the input multiplane image stack including a plurality of texture images and a corresponding plurality of alpha images, ones of the alpha images including pixel values representative of transparency of corresponding pixels in respective ones of the texture images. Disclosed example apparatus also include a compressed image encoder to at least one of (i) convert the plurality of texture images to a single composite texture image to generate a compressed multiplane image stack, or (ii) convert the plurality of alpha images to a single composite alpha image to generate the compressed multiplane image stack. In some disclosed examples, the interface is to output the compressed multiplane image stack.

Multi-plane image compression

Examples described herein relate to a system that includes a central processing unit; a trusted execution environment (TEE); and a graphics processing system. In some examples, the central processing unit is to process homomorphically encrypted video game object data. In some examples, the TEE is to transpose the processed homomorphically encrypted object data to a second encryption format. In some examples, the graphics processing system is to perform a graphics processing pipeline operation on the object data in the second encryption format and provide rendered image data of the video game to a buffer. In some examples, the TEE is to receive homomorphic decryption keys and transpose the processed homomorphically encrypted object data to a second encryption format based on the homomorphic decryption keys. In some examples, the system is to inform a gaming server of a change to object data received from the gaming server to identify cheating.

Anti-cheat game technology in graphics hardware

Embodiments described herein include, software, firmware, and hardware logic that provides techniques to perform arithmetic on sparse data via a systolic processing unit. Embodiment described herein provided techniques to detect zero value elements within a vector or a set of packed data elements output by a processing resource and generate metadata to indicate a location of the zero value elements within the plurality of data elements.

Sparse optimizations for a matrix accelerator architecture

Often when there is a glare on a display screen the user may be able to mitigate the glare by tilting or otherwise moving the screen or changing their viewing position. However, when driving a car there are limited options for overcoming glares on the dashboard, especially when you are driving for a long distance in the same direction. Embodiments are directed to eliminating such glare. Other embodiments are related to mixed reality (MR) and filling in occluded areas.

Glare and occluded view compensation for automotive and other applications

One embodiment provides a graphics processor comprising a block of execution resources, a cache memory, a cache memory prefetcher, and circuitry including a programmable neural network unit, the programmable neural network unit comprising a network hardware block including circuitry to perform neural network operations and activation operations for a layer of a neural network, the programmable neural network unit addressable by cores within the block of graphics cores and the neural network hardware block configured to perform operations associated with a neural network configured to determine a prefetch pattern for the cache memory prefetcher.

Graphics architecture including a neural network pipeline

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache coupled to the processing resources. The cache controller is configured to control cache priority by determining whether default settings or an instruction will control cache operations for the cache.

Systems and methods for improving cache efficiency and utilization

Methods and apparatus relating to techniques for multi-tile memory management. In an example, a graphics processor includes an interposer, a first chiplet coupled with the interposer, the first chiplet including a graphics processing resource and an interconnect network coupled with the graphics processing resource, cache circuitry coupled with the graphics processing resource via the interconnect network, and a second chiplet coupled with the first chiplet via the interposer, the second chiplet including a memory-side cache and a memory controller coupled with the memory-side cache. The memory controller is configured to enable access to a high-bandwidth memory (HBM) device, the memory-side cache is configured to cache data associated with a memory access performed via the memory controller, and the cache circuitry is logically positioned between the graphics processing resource and a chiplet interface.

Multi-tile memory management

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received.

Systems and methods for cache optimization

Apparatuses including a graphics processing unit, graphics multiprocessor, or graphics processor having an error detection correction logic for cache memory or shared memory are disclosed. In one embodiment, a graphics multiprocessor includes cache or local memory for storing data and error detection correction circuitry integrated with or coupled to the cache or local memory. The error detection correction circuitry is configured to perform a tag read for data of the cache or local memory to check error detection correction information.

Systems and methods for error detection and control for embedded memory and compute elements

Embodiments are generally directed to methods and apparatuses of spatially sparse convolution module for visual rendering and synthesis. An embodiment of a method for image processing, comprising: receiving an input image by a convolution layer of a neural network to generate a plurality of feature maps; performing spatially sparse convolution on the plurality of feature maps to generate spatially sparse feature maps; and upsampling the spatially sparse feature maps to generate an output image.

Method and apparatus of spatially sparse convolution module for visual rendering and synthesis

Systems and methods for improving cache efficiency and utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Methods and apparatus relating to techniques for multi-tile memory management. In an example, an apparatus comprises a cache memory, a high-bandwidth memory, a shader core communicatively coupled to the cache memory and comprising a processing element to decompress a first data element extracted from an in-memory database in the cache memory and having a first bit length to generate a second data element having a second bit length, greater than the first bit length, and an arithmetic logic unit (ALU) to compare the data element to a target value provided in a query of the in-memory database. Other embodiments are also disclosed and claimed.

Embodiments are generally directed to multi-tile graphics processor rendering. An embodiment of an apparatus includes a memory for storage of data; and one or more processors including a graphics processing unit (GPU) to process data, wherein the GPU includes a plurality of GPU tiles, wherein, upon geometric data being assigned to each of a plurality of screen tiles, the apparatus is to transfer the geometric data to the plurality of GPU tiles.

Multi-tile graphics processor rendering

Embodiments described herein include software, firmware, and hardware that provides techniques to enable deterministic scheduling across multiple general-purpose graphics processing units. One embodiment provides a multi-GPU architecture with uniform latency. One embodiment provides techniques to distribute memory output based on memory chip thermals. One embodiment provides techniques to enable thermally aware workload scheduling. One embodiment provides techniques to enable end to end contracts for workload scheduling on multiple GPUs.

Graphics processor operation scheduling for deterministic latency

Systems and methods for cache utilization are disclosed. In one embodiment, a graphics processor includes processing resources to perform graphics operations and a cache controller of a cache memory that is coupled to the processing resources. The cache controller is configured to set an initial aging policy using an aging field based on age of cache lines within the cache memory and to determine whether a hint or an instruction to indicate a level of aging has been received. In one embodiment, the cache memory configured to be partitioned into multiple cache regions, wherein the multiple cache regions include a first cache region having a cache eviction policy with a configurable level of data persistence.

Growing community of inventors

Davis, CA, United States of America

Scott R Janus