Nvidia Corporation

Scott Phillip Cutler

Rouslan Lyubomirov Dimitrov

Sau Yan Keith Li

Viktor Grigoryevich Vandanov

James Howard

Jonah Matthew Alben

Karan Mehra

Praveen Krishnamurthy

Jeff Pool

Chris Amsinck

A performance metrics of a receiver is obtained using frames of an application hosted by a server that are received via a network. The one or more performance metrics include information indicative of a current occupancy of a frame buffer corresponding to the receiver and information indicative of a target occupancy of the frame buffer corresponding to the receiver. The frame buffer of the receiver is used to queue frames of the application for display. A frame rate associated with rendering at least one next frame of the application is adjusted using the one or more performance metrics of the receiver to control population of the frame buffer. Subsequent frames of the application hosted by the server are rendered using the adjusted frame rate. Upon rendering the subsequent frames, the server sends the subsequent frames to the receiver for display.

Dynamically reducing stutter and latency in video streaming applications

A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.

Architecture and algorithms for data compression

A system and method are provided for reducing the number of depth clear operations in a hardware graphics pipeline. Initially, a frame count is stored into a frame buffer associated with the hardware graphics pipeline. The stored frame count is associated with a pixel. A depth clear operation is then performed based at least in part on the frame count utilizing the hardware graphics pipeline.

System and method for avoiding depth clears using a stencil buffer

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San Jose, CA, United States of America

Scott Phillip Cutler