Intel Corporation

Scott P Bobholz

Malini Krishnan Bhandaru

Eric J DeHaemer

Vivek Garg

Raghunandan Makaram

Sergiu D Ghetie

Wojciech S Powiertowski

Scott J Cape

Jason W Brandt

Joseph Nuzman

Lihu Rappoport

Robert S Chappell

Deepak K Gupta

James R Vash

Jared Warner Stark, Iv

Rodrigo Branco

David T Mayo

Sagar V Dalvi

Ariel Sabba

Yair Berger

Gilad Holzstein

Martin Guy Dixon

Ankush Varma

Mahesh S Natu

Vasudevan Srinivasan

Ian M Steiner

Sailesh Kottapalli

Allen Jay Baum

Sham M Datta

Hisham Shafi

Neeraj S Upasani

Matthew M Bace

Christopher Allan Poirier

Tracy Garrett Drysdale

Monica C Wong-Chan

Chris Poirier

Arkadiusz Berent

Jeff Wiedemeier

Chinmay Ashok

Vasuki Chilukuri

Chukwunenye S Nnebe

Eric Dehaemer

Vinila Rose

A Leonard Brown

Won Lee

Samuel W Ho

Keshav Murty

Shaila R Murty

Yogesh Bijlani

Atanas K Iwanow

Lorie Wigle

Jason Kennedy

Methods and apparatuses relating to mitigations for speculative execution side channels are described. Speculative execution hardware and environments that utilize the mitigations are also described. For example, three indirect branch control mechanisms and their associated hardware are discussed herein: (i) indirect branch restricted speculation (IBRS) to restrict speculation of indirect branches, (ii) single thread indirect branch predictors (STIBP) to prevent indirect branch predictions from being controlled by a sibling thread, and (iii) indirect branch predictor barrier (IBPB) to prevent indirect branch predictions after the barrier from being controlled by software executed before the barrier.

Apparatuses and methods for speculative execution side channel mitigation

Methods and apparatus for restricted deployment of targeted processor firmware updates. During a patch enabling per-work flow, service entitlement license information comprising one of more service entitlements is generated and provisioned on one or more computing platforms. A restricted deployment microcode (uCode) update release (aka uCode patch) targeted for platforms having CPUs and/or XPUs with certain part identifier is sent to the one or more platforms. Run-time software and/or firmware on the platforms are executed to access the provisioned service entitlement license information, which is used to authentic and verify the restricted deployment uCode update release using a service entitlement having a part identifier associated with the platform's CPU. In one solution, authentication is performed using a hash-matching scheme and verification is used to verify the platform is properly licensed to load uCode included in the restricted deployment microcode (uCode) update release into the CPU.

Techniques for restricted deployment of targeted processor firmware updates

In one embodiment, a multicore processor includes cores that can independently execute instructions, each at an independent voltage and frequency. The processor may include a power controller having logic to provide for configurability of power management features of the processor. One such feature enables at least one core to operate at an independent performance state based on a state of a single power domain indicator present in a control register. Other embodiments are described and claimed.

Multicore processor with a control register storing an indicator that two or more cores are to operate at independent performance states

Techniques and apparatuses for issuance of license upgrades for hardware components in the field, as well as the hardware components, are described. In one embodiment, for example an apparatus may include processor circuitry and memory in communication with the processor circuitry, wherein the memory contains a configuration data block and license data block, the configuration data block being read from the memory via a licensing apparatus and the licensing data block being written to the memory by the licensing apparatus. The processor may include executable code to process the licensing data block to facilitate an upgrade of the capabilities of the processor circuitry.

System and method for reconfiguring and deploying soft stock-keeping units

Configuring power management functionality in a processor

A method and apparatus for per core performance states in a processor. Per Core Performance States (PCPS) refer to the parallel operating of individual cores at different voltage and/frequency points. In one embodiment of the invention, the processor has a plurality of processing cores and a power control module that is coupled with each of the plurality of processing cores. The power control module facilitates each processing core to operate at a different performance state from the other processing cores. By allowing its cores to have per core performance state configuration, the processor is able to reduce its power consumption and increase its performance.

Method and apparatus for per core performance states

In one embodiment, the present invention includes a method for determining whether a number of stalled cores of a multicore processor is greater than a stall threshold. If so, a recommendation may be made that an operating frequency of system agent circuitry of the processor be increased. Then based on multiple recommendations, a candidate operating frequency of the system agent circuitry can be set. Other embodiments are described and claimed.

Dynamically controlling interconnect frequency in a processor

A processor is described that includes a processing core and a plurality of counters for the processing core. The plurality of counters are to count a first value and a second value for each of multiple threads supported by the processing core. The first value reflects a number of cycles at which a non sleep state has been requested for the first value's corresponding thread, and, a second value that reflects a number of cycles at which a non sleep state and a highest performance state has been requested for the second value's corresponding thread. The first value's corresponding thread and the second value's corresponding thread being a same thread.

Processor having per core and package level P0 determination functionality

Configuring power management functionality in a processor including a plurality of cores by utilizing a register to store a power domain indicator

Systems and methods for enabling Reliability, Availability & Serviceability features after launching a secure environment under the control of LaGrande Technology (LT), or comparable security technology, without compromising security are provided. In one embodiment, the method comprises adding at least one specific capability to a processor to enable at least one of CPU hot-plug, CPU migration, CPU hot removal and capacity on demand.

Supporting advanced RAS features in a secured computing system

Growing community of inventors

Bolton, MA, United States of America

Scott P Bobholz