Xilinx, Inc.

National Semiconductor Corporation

Scott O Frake

F Erich Goetting

Venu M Kondapalli

Steven P Young

Jennifer Wong

David P Schultz

Peter H Alfke

Raymond C Pang

Jane W Sowards

Stephen M Trimberger

Kameswara K Rao

Schuyler E Shimanek

Alvin Y Ching

Philip D Costello

Jason R Bergendahl

Wilson Kaming Yee

Roger D Carpenter

James L McManus

Mark W Knecht

Erich F Goetting

A low pass filter (LPF) is provided that smoothes and significantly slows any change in its input voltage. The capacitance of the LPF is provided by an NMOS transistor having its source and drain tied to ground. The resistance of the LPF is provided by a plurality of series-connected PMOS transistors. The gates of the PMOS transistors are coupled to ground and therefore these transistors are conducting. The PMOS transistors are fabricated in a floating well. Therefore, the LPF eliminates any capacitive coupling between a voltage supply and the well. Thus, any variation in the supply voltage fails to affect adversely the functioning of the PMOS transistors. Thus, the LPF of the present invention can advantageously smooth and significantly slow any change in its input voltage. In one embodiment, the input voltage is a reference voltage. In this manner, a voltage regulator, which receives the filtered reference voltage from the LPF, in turn provides a significantly more constant regulated voltage to the internal circuits of the IC. Thus, the present invention advantageously minimizes the possibility of a malfunction in a digital system due to a variation in the regulated voltage.

Low pass filter

An apparatus and method for enabling hot swapping of programmable logic devices (PLDs) and boards containing PLDs is provided. If the hot swap capability is desired, a hot swap terminal on the PLD is set to facilitate a floating state on the input/output pad of the PLD. Further, the input buffer and the output buffer of the PLD are disabled. In one embodiment, a predetermined voltage is provided on the output terminal of the input buffer. In this configuration, the hot swap circuit eliminates any leakage current, ensures no static current occurs, and provides appropriate signals to the internal circuits of the PLD.

Method and system for PLD swapping

The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage and/or a single output voltage supply is applied to each IOB, with the IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

FPGA with a plurality of input reference voltage levels

A PLD can be manufactured to include power supply lines from two sources so that a portion of the PLD can be backed up with a battery when power to the PLD is removed. A switch that supplies power to the backed up portion of the PLD receives power from both an external power supply and from the battery, and detects voltage level of the external power supply, switching to battery power when voltage from the external power supply is not sufficient.

Programmable logic device with partial battery backup

It is sometimes desirable to encrypt a design for loading into a PLD so that an attacker may not learn and copy the design as it is being copied into the PLD. According to the invention, the encrypted design is decrypted by a key or keys within the PLD that are preserved when power is removed by either being stored in nonvolatile memory or by being backed up with a battery that switches into operation when the power is removed from the PLD.

Nonvolatile/battery-backed key in PLD

A clock gating circuit is provided for a logic device that reduces device resource requirements, eliminates the need for users to define their own clock gating circuit, and eliminates undesirable clock signal disturbances, such as glitches and runt pulses. In one embodiment, the clock gating circuit includes an input terminal for receiving an input clock signal; an input terminal for receiving a clock enable signal; a storage latch coupled to receive the input clock signal and the clock enable signal, and in response, provide a clock gate control signal; and a logic gate coupled to receive the input clock signal and the clock gate control signal. The logic gate selectively routes the input clock signal in response to the clock gate control signal, thereby providing an output clock signal.

Clock-gating circuit for reducing power consumption

FPGA with a plurality of input reference voltage levels grouped into sets

FPGA with a plurality of I/O voltage levels

Described are delay circuits that are relatively insensitive to changes in temperature and supply voltage. A delay circuit includes at least one inverter circuit made up of a pair of transistors. The inverter responds to voltage changes on the input terminal by providing corresponding inverse changes on the output terminal. The speed at which the inverter responds to voltage changes on the input terminal depends upon the ability of one or both transistors to conduct current to or from the output terminal. The ability of one or both transistors in the inverter to move charge to or from the output terminal is restricted to reduce the switching speed of the inverter, thus imposing a delay on the input signal. Further, the restricted current is provided at a reference level that is relatively insensitive to temperature changes and supply-voltage fluctuations.

Delay circuit with temperature and voltage stability

The invention comprises a configurable input/output buffer for an FPGA that can be configured to comply with any of two or more different I/O standards. Factors such as output drive strength, receiver type, output driver type, and output signal slew rate are configurably controlled. In some embodiments, the input power supply and the output power supply can be different from the core voltage supply. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad are configurably connected to the input reference voltage line. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines. According to another aspect of the invention, a single input reference voltage or a single output voltage supply is applied to each Input/Output Block (IOB), with IOBs grouped into sets. Each set of IOBs has a separate input reference voltage and/or a separate output voltage supply.

Input/output buffer supporting multiple I/O standards

A flip-flop includes non-volatile storage of a bit for encryption purposes or other applications. The non-volatile bit remains in the flip-flop, substantially unaltered, irrespective of normal flip-flop operation, and is available to be recalled whenever it is needed. The flip-flop is implemented using a pair of CMOS cells. Each cell includes a floating gate formed by connecting the gates of an n-mos transistor and a p-mos transistor. One of the two floating gates is selectively charged by hot electron injection, thereby raising the threshold of that cell. Depending upon which of the two cells is programmed by this process, the flip-flop outputs a logic one or a logic zero during a recall mode.

CMOS flip-flop having non-volatile storage

The invention comprises an FPGA having a plurality of input reference voltages and/or output voltage supplies. In one embodiment, two or more differential amplifiers in the same configurable input buffer use different input reference voltages. According to a second aspect of the invention, the I/O pad line is configurably connected to the input reference voltage line, so that any configurable Input/Output Block (IOB) can be used to supply the input reference voltage. According to a third aspect of the invention, the reference input of an I/O is configurably connected to any of two or more input reference voltage lines.

For a memory cell comprising a latch with cross-coupled inverters and an n-channel access transistor, the inverter that can contend with the access transistor is connected not between power and ground but between power and a transistor that disconnects the inverter from ground when the memory cell is being written. This allows transistors in the memory cell to be small and still function properly, without requiring that a port be provided for the complement of the data signal. The invention is important when there are several write ports to the memory cell and the addressing overhead is significant.

Write-assisted memory cell and method of operating same

A capacitor is formed in three adjacent conductive layers of a semiconductor integrated circuit chip. A first plate of the capacitor is formed in the middle layer. A second plate is formed in the upper and lower layers plus a small portion of the middle layer which interconnects the upper and lower layers and forms a U-shaped structure surrounding the first plate. These capacitors are preferably formed in pairs with the first plates interconnected. The second plates may be connected to different voltage supplies to form a capacitive voltage divider.

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Cupertino, CA, United States of America

Scott O Frake