International Business Machines Corporation

Scott Michael Willenborg

Ronald Edward Fuhs

Claude Basso

Jean Louis Calvignac

Colin Beaton Verrilli

Nathaniel Paul Sellin

Fabrice Jean Verplanken

Natarajan Vaidhyanathan

Chih-Jen Chang

Philippe Damon

Steven Lyn Rogers

Paul E Schardt

Scott Douglas Clark

Aj KleinOsowski

Thomas M Armstead

John Hubert Klaus

Ravi Kumar Arimilli

William John Starke

Daniel Frank Moertl

Steven Mark Thurber

Lakshminarayana Baba Arimilli

Bartholomew Blaner

Randal Craig Swanberg

Danny Marvin Neal

Harvey Gene Kiel

Adalberto Guillermo Yanes

Kyle Alan Lucke

Satya Prakash Sharma

Kent Harold Haselhorst

Curtis Carl Wollbrink

Andrew P Wack

Mark S Fredrickson

Jeffrey Joseph Ruedinger

Matthew Roger Ellavsky

Ryan Scott Haraden

Juergen Saalmueller

Calvin Charles Paynton

Jeremy T Ekman

Timothy Lindquist

Pat Allen Buckland

Blake Johnson

Bruce B Winter

Thomas Alexander

Zachary Kauffman

Systems, compute-implemented methods, and computer program products to facilitate automated waveform validation are provided. According to an embodiment, a system can comprise a processor that executes computer executable components stored in memory. The computer executable components comprise a waveform comparison component that compares a digital conversion of an analog signal to a reference signal.

Automated waveform validation

Embodiments are provided for centralized control of execution of a quantum program. In some embodiments, a system can include a processor that executes computer-executable components stored in memory. The computer-executable components include a synchronization component that causes multiple controller devices remotely located relative to the system to be synchronized with one another and the system. The computer-executable components also include an ingestion component that accesses measurement data resulting from one or more measurements at respective qubit devices. The computer-executable components further include a composition component that generates, using the measurement data, one or more control messages for respective second controller devices of the multiple controller devices.

Centralized control of execution of quantum program

A processor core of a data processing system, in response to a first instruction, generates a copy-type request specifying a source real address and transmits it to a lower level cache. In response to a second instruction, the processor core generates a paste-type request specifying a destination real address associated with a memory-mapped device and transmits it to the lower level cache. In response to the copy-type request, the lower level cache copies a data granule from a storage location specified by the source real address into a non-architected buffer. In response to the paste-type request, the lower level cache writes the data granule from the non-architected buffer to the memory-mapped device. In response to receipt of the data granule, the memory-mapped device stores the data granule in a queue in the system memory associated with a hardware device of the data processing system.

Memory move instruction sequence targeting an accelerator switchboard

A verification environment enables verification of runtime switch-over&#x2014;i.e., a switch-over without restarting the device under test&#x2014;between multiple I/O protocols that share a same physical interface. The device under test can be a switch unit having multiple logical protocol processing units and a logical protocol multiplexor. The verification environment includes a switch-over detector which monitors the state of the device under test, and a switch-over controller that controls the switch-over sequence by pausing and re-starting traffic on all or specific protocol drivers of the verification environment.

Verifying runtime switch-over between multiple I/O protocols on shared I/O connection

Embodiments herein describe a switchboard coupled to a system bus in an integrated circuit for managing the flow of data between different entities coupled to the bus (e.g., processing cores, accelerators, memory controllers, input/output (I/O) interfaces, and the like). The switchboard is a hardware module that may be tasked with assigning different system bus addresses (or range of addresses) to each of the entities coupled to the bus. These addresses may be unique such that each entity can be uniquely identified by its assigned address. The address space of the system bus also includes managed address that are reserved&#x2014;i.e., are not assigned to any particular entity. The switchboard is tasked with assigning the managed addresses (also referred to as virtual channels) to an entity which can be used to enable direct communication between hardware entities using the system bus.

Communicating in an integrated circuit using hardware-managed virtual channels

A system is disclosed for concurrently processing order sensitive data packets. A first data packet from a plurality of sequentially ordered data packets is directed to a first offload engine. A second data packet from the plurality of sequentially ordered data packets is directed to a second offload engine, wherein the second data packet is sequentially subsequent to the first data packet. The second offload engine receives information from the first offload engine, wherein the information reflects that the first offload engine is processing the first data packet. Based on the information received at the second offload engine, the second offload engine processes the second data packet so that critical events in the processing of the first data packet by the first offload engine occur prior to critical events in the processing of the second data packet by the second offload engine.

Multi-threaded packet processing

A system is disclosed for fetching control instructions for a direct memory access (DMA) engine shared between a plurality of threads. For a data transfer from a first thread by a DMA engine, the DMA engine fetches and processes a predetermined number of control instructions (or work queue elements) for the data transfer, each of the control instructions including an amount and location of data to transfer. The DMA engine determines a total amount of data transferred as a result of the data transfer. The DMA engine then determines a difference between the total amount of data transferred and a threshold amount of data, wherein the threshold amount of data indicates a preferred amount of data to be transferred for the first thread. The predetermined number of control instructions to fetch is updated based on the determined difference.

Prefetching for a shared direct memory access (DMA) engine

A method for designing integrated circuits uses clock signal interleaving to reduce the likelihood of a soft error arising from an upset in a clock distribution network. At least two circuits in a circuit description are identified as being sensitive to radiation, and different clock distribution nodes are assigned to the two circuits. Several exemplary implementations are disclosed. The second circuit may be a redundant replica of the first circuit, such as a reset circuit. The first and second circuits may be components of a modular redundant circuit such as a triple modular redundancy flip-flop. The first circuit may include a set of data bits for an entry of a storage array such as a register or memory array, and the second circuit may include a set of check bits associated with the entry.

Radiation tolerance by clock signal interleaving

Apparatus for providing a checksum in a network transmission. In one aspect of the invention, a checksum for a packet to be transmitted on a network is determined by retrieving packet information from a storage device, the packet information to be included in the packet to be transmitted. A blind checksum value is determined based on the retrieved packet information, and the blind checksum value is adjusted to a protocol checksum based on descriptor information describing the structure of the packet. The protocol checksum is inserted in the packet before the packet is transmitted.

Apparatus for blind checksum and correction for network transmissions

A method of speculative credit data flow control includes defining a low watermark value as a function of a number of open buffers in a receiving unit; receiving a data packet from a sending unit; determining whether the data packet includes a packet delay indicator; defining a first speculative credit value responsive to receiving the packet delay indicator; defining a second speculative credit value as a function of the first speculative credit value added to a regular credit value; generating a flow control packet including the second speculative credit value; and sending the flow control packet to the sending unit.

Speculative credit data flow control

A method of designing a layout of an integrated circuit for increased radiation tolerance by ensuring that any critical components (those deemed particularly sensitive to radiation-induced soft errors) are at spacings greater than a predetermined threshold based on particle migration within the silicon substrate. The method starts with an initial placement, identifies the objects for which radiation tolerance is desired, determines whether any of those objects and, if so, moves the relevant objects to increase the spacing. An exemplary threshold for contemporary CMOS device technologies is 5 &#x3bc;m. The objects can be moved by vertically and/or horizontally shifting away from a reference point of the integrated circuit. The critical objects may include triplicated (redundant) structures, clock control latches, or a reset bit. The method can be used in conjunction with other placement optimizations such as area, power and timing.

Method for radiation tolerance by automated placement

Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.

Network communications for operating system partitions

In a first aspect, a first method of transmitting a data packet is provided. The first method includes the steps of (1) for each connection from which a data packet may be transmitted, storing header data corresponding to the connection; (2) employing a user application to form header and payload data of a packet, wherein the user application is associated with a connection from which the packet is to be transmitted; and (3) while transmitting the packet, comparing one or more portions of the packet header data with the header data corresponding to the connection with which the user application is associated. Numerous other aspects are provided.

Methods and apparatus for improving security while transmitting a data packet

A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.

System and method for computing a blind checksum in a host ethernet adapter (HEA)

Growing community of inventors

Stewartville, MN, United States of America

Scott Michael Willenborg