L-3 Communications Integrated Systems L.p.

Scott Michael Burkart

Matthew Pascal DeLaquil

Deepak Prasanna

Joshua David Anderson

Antone Lee Kusmanoff

Jonathan E Brown

Gerald Lothair Fudge

Bryan Lloyd Westcott

A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.

System and method for storing a sparse matrix

An adaptive wakeup methodology may be implemented to allow an radio frequency identification (RFID) tag to stay synchronized with periodic radio frequency (RF) interrogator polling signal while at the same time optimizing power consumption. A receiver (or transceiver) component of a RFID tag may only be operated when an interrogator polling signal is expected, and in a manner that reduces the amount of time between when the receiver or transceiver is turned on and when the interrogator polling signal is received (i.e., the receive buffer time). At other times, the RFID tag may be placed in a low power consumption sleep state. The amount of time that the RFID tag spends in such a low power sleep state before waking and receiving the following interrogator polling signal may also be optionally adjusted, e.g., to fit characteristics of a given situation and/or to re-synchronize a given aRFID tag with first band transmissions from an aRFIDI.

Synchronization of devices in a RFID communications environment

RF sampling receivers are disclosed that employ multiple sampling clocks to produce multiple projections. In operation, a Nyquist folded receiver (NYFR) may be implemented that utilizes at least one modulated sampling clock in combination with one or more other modulated or non-modulated sampling clocks to identify received signals. In such an embodiment, one or more clock modulations may be used to induce frequency modulations that are Nyquist zone dependent, and multiple Nyquist zones may be aliased together while still allowing for signals from different Nyquist zones to be separated and identified.

Multiple projection sampling for RF sampling receivers

Systems and methods for data separation, which may be employed to receive and process RFID tag data in RF signal environments where multiple RFID tags are tracked, localized and/or employed to transmit information. The disclosed systems and methods may be implemented for data separation in a high density aRFID environment using RFID tags in combination with spatial and/or frequency separation.

Data separation in high density environments

A mobile communication device includes a processor; a data acquisition device for acquiring data and providing it to the processor; a transceiver for transmitting at least some of the acquired data to an external device; and a low-power clock. The low-power clock counts down a random delay time period and temporarily shifts the processor and the transceiver from low-power sleep modes to active wake modes so that the processor and transceiver can transmit at least some of the acquired data to the external device while in their active wake modes.

Mobile communication device and communication method

Application Specific Integrated Circuit ('ASIC') devices, such as Field Programmable Gate Arrays ('FPGAs'), may be interconnected using serial I/O connections, such as high speed multi-gigabit serial transceiver (&#x201c;MGT&#x201d;) connections. For example, serial I/O connections may be employed to interconnect a pair of ASICs to create a high bandwidth, low signal count connection, and in a manner so that any given pair of multiple ASIC devices on a single circuit card may communicate with each other through no more than one serial data communication link connection step. A reconfigurable hardware architecture (&#x201c;RHA&#x201d;) may be configured to include a communications infrastructure that uses a high-bandwidth packet router to establish standard communications protocols between multiple interfaces and/or multiple devices that may be present on a single circuit card. Dynamically-sized data packets, sized in accordance with the amount of data ready to be sent, are transferred between the devices and/or interfaces on the card.

Systems and methods for sending data packets between multiple FPGA devices

A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.

Growing community of inventors

Royse City, TX, United States of America

Scott Michael Burkart