Fujitsu Corporation

Scott McLeod

Nikola Nedovic

William Warren Walker

Shuo-Chun Kao

In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.

Method and apparatus for implementing slice-level adjustment

In one embodiment, a method includes applying, by a transimpedance amplifier at a receiving end of a communication link, equalization to a signal carried by the communication link at the receiving end of the communication link.

Transimpedance amplifier with equalization

An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased.

Bandwidth extension of an amplifier

A circuit that includes an amplifier circuit with an input impedance due to an input resistance and an input capacitance of the amplifier circuit. The input impedance of the amplifier circuit may vary with frequency. The amplifier circuit may include an amplifier and a feedback circuit configured to provide feedback to the amplifier and to maintain the input impedance at a specified value at a selected frequency by increasing the input resistance of the amplifier circuit at the selected frequency.

Impedance adjustments in amplifiers

In one embodiment, a method includes, in response to assertion of a write-enable signal at a memory array that comprises a plurality of words, sequentially and at a first clock frequency writing data to the memory array starting at a beginning of the memory array until the memory array is full. The method includes, independent of the writing of data to the memory array, asynchronously and at a second clock frequency that is slower than the first clock frequency reading data from the memory array based on read addresses received at the memory array.

Sequential-write, random-read memory

In one embodiment, a transmitter can bias a vertical-cavity surface-emitting laser (VCSEL) coupled to an optical medium. The biasing of the VCSEL determines at least in part an optical power output by the VCSEL to the optical medium. The transmitter can also modulate the VCSEL with data to transmit the data optically through the optical medium to a receiver; receive from the receiver through a feedback channel an error vector representing a degradation in performance of the VCSEL sensed by the receiver or an instruction vector comprising one or more coefficients for use in biasing the VCSEL; and adjust the biasing of the VCSEL based on the error vector or the instruction vector to regulate the optical power output by the VCSEL to the optical medium.

Regulating a vertical-cavity surface-emitting laser (VCSEL)-based optical communication link

In one embodiment, a method includes generating two or more clock signals, sequentially selecting each one of the clock signals, and adjusting the respective clock duty cycle of the selected one of the clock signals until it substantially matches a predetermined clock duty cycle. The adjustment of the respective clock duty cycle includes generating a control signal based on the respective clock duty cycle, generating a duty-cycle-distortion (DCD) correction signal based on the control signal, adjusting the respective clock duty cycle of the selected one of the clock signals based on the DCD correction signal, and adjusting the control and DCD correction signals and re-adjusting the respective clock duty cycle of the selected one of the clock signals until the respective clock duty cycle of the selected one of the clock signals substantially matches the predetermined clock duty cycle.

Clock signal correction

In one embodiment, a method includes receiving, at a filter comprising a Miller amplifier, a differential data signal output by a limiting amplifier (LA), the data signal comprising an output direct current (DC) offset resulting at least in part from a threshold-adjustment signal applied to the LA or an intrinsic DC offset caused by physical characteristics of the LA. In one embodiment, the method additionally includes generating a compensation signal based on the threshold-adjustment signal, a polarity of the compensation signal being opposite a polarity of the threshold-adjustment signal or the DC offset, a magnitude of the compensation signal being a function of the magnitude of the threshold-adjustment signal. In one embodiment, the method further includes introducing the compensation signal to an internal node of the Miller amplifier to compensate for the DC offset to keep one or more amplifier stages of the Miller amplifier in their linear operating regions.

Growing community of inventors

Los Gatos, CA, United States of America

Scott McLeod