University of Michigan

Arm Limited

Samsung Electronics Co., Ltd.

Parakinetics Inc.

Scott Mahlke

Andrew Lukefahr

Krisztian Flautner

Reetuparna Das

Shruti Padmanabha

Nathan Clark

Stuart David Biles

Jiecao Yu

Ganesh Suryanarayan Dasika

Reetuparnda Das

Ankit Sethia

David Palframan

Trevor N Mudge

Suk-jin Kim

Daryl Wayne Bradley

Ki-seok Kwon

Hyunchul Park

Yong-Jun Park

Donghoon Yoo

Yongjun Park

Sukjin Kim

Heejun Shim

David I August

Sami Yehia

Mojtaba Mehrara

Jason Andrew Blome

John Kloosterman

Jonathan Beaumont

Davoud Anoushe Jamshidi

Jonathan Bailey

Jason Jong Kyu Park

Kevin C Fan

Jae Wook Lee

Amir Hormati

Subject matter disclosed herein may relate to storage and/or processing of signals and/or states representative of neural network parameters in a computing device, and may relate more particularly to compressing signals and/or states representative of neural network nodes in a computing device.

Systems and devices for compressing neural network parameters

Subject matter disclosed herein may relate to storage of signals and/or states representative of parameters in a computing device, and may relate more particularly to storage of signals and/or states representative of neural network parameters in a computing device.

Systems and devices for formatting neural network parameters

A method, apparatus, and CRM that detect repetition of an out-of-order execution schedule for a group of instructions executed by an out-of-order processor. Data indicative of at least one performance metric for an instance of execution of said group of instructions by the out-of-order processor is determined. The determined data are compared with previous data of the at least one performance metric for at least one previous instance of execution of the group of instructions by the out-of-order processor. Repetition of the out-of-order execution schedule is detected dependent on the comparison.

Method of detecting repetition of an out-of-order execution schedule, apparatus and computer-readable medium

A technique is provided for processing thread groups, each thread group having associated program code comprising a plurality of regions that each require access to an associated plurality of registers providing operand values for the instructions of that region. Capacity management circuitry is arranged, for a thread group having a region of the associated program code that is ready to be executed, to perform an operand setup process to reserve sufficient storage elements within an operand staging unit to provide the associated plurality of registers, and to cause the operand value for any input register to be preloaded into a reserved storage element allocated for that input register, an input register being a register whose operand value is required before the region can be executed. Scheduling circuitry selects for processing a thread group for which the operand setup process has been performed in respect of the region to be executed.

Dynamically allocating storage elements to provide registers for processing thread groups

Apparatus and a corresponding method for controlling a transition between use of first processing circuitry and second processing circuitry to execute program instructions are provided. Transition monitoring storage selects an entry for a load program instruction executed during the transition in dependence on a memory address from which a value is to be loaded and stores a program order timestamp for the load program instruction, unless a valid previously stored program order timestamp in the entry precedes the program order timestamp. Thus the oldest timestamp of an load instruction executed in the transition is held. At either the start or end (or both) of the transition the content of the transition monitoring storage is cleared. When a store program instruction is executed during the transition and when a further program order timestamp for the store program instruction indicates that the store program instruction precedes in program order a load program instruction already executed in the transition, program instructions which follow the store program instruction in the first and second processing circuitry are squashed and re-executed. Data hazards which could otherwise arise during the transition are thus avoided by the use of transition monitoring storage which is nevertheless conveniently small.

Controlling transition between using first and second processing circuitry

An apparatus for processing data includes first execution circuitry, such as an out-of-order processor, and second execution circuitry, such as an in-order processor. The first execution circuitry is of higher performance but uses more energy than the second execution circuitry. Control circuitry switches between the first execution circuitry being active and the second execution circuitry being active. The control circuitry includes prediction circuitry which is configured to predict a predicted identity of a next sequence of program instructions to be executed in dependence upon a most recently executed sequence of program instructions and then in dependence upon this predicted identity to predict a predicted execution target corresponding to whether the next sequence of program instructions should be executed by the first execution circuitry or the second execution circuitry.

Recording performance metrics to predict future execution of large instruction sequences on either high or low performance execution circuitry

A multithreaded data processing system performs processing using resource circuitry which is a finite resource. A saturation signal is generated to indicate when the resource circuitry is no longer able to perform processing operations issued to it. This saturations signal may be used to select a scheduling algorithm to be used for further scheduling, such as switching to scheduling from a single thread as opposed to round-robin scheduling from all of the threads. Re-execution queue circuitry is used to queue processing operations which have been enabled to be issued so as to permit other processing operations which may not be blocked by the lack of use of circuitry to attempt issue.

Issue control for multithreaded processing

Provided is a method and apparatus of selecting a preemption technique for a computation unit included in a processor to execute a second task before the at least one computation unit finishes executing a first task. The method includes receiving a preemption request, predicting a cost of preemption techniques based on a progress of the first task until receipt of the preemption request, and selecting one of the preemption techniques based on the predicted cost.

Method and apparatus for selecting preemption technique

A data processing apparatus includes a first execution mechanism, such as an out-of-order processing circuitry, and a second execution mechanismsuch as an in-order processing circuitry. Switching control circuitry controls switching between which of the first execution circuitry and the second execution circuitry is active at a given time. Latency indicating signals indicative of the latency associated with a candidate switching operation to be performed are supplied to the switching control circuitry and used to control the switching operation. The control of the switching operation may be to accelerate the switching operation, prevent the switching operation, perform early architectural state data transfer or other possibilities.

Control of switching between executed mechanisms

This follows a data processing system comprising multiple GPUs includes instruction queue circuitry storing data specifying program instructions for threads awaiting issue for execution. Instruction characterization circuitry determines one or more characteristics of the program instructions awaiting issue within the instructional queue circuitry and supplies this to operating parameter control circuitry. The operating parameter control circuitry alters one or more operating parameters of the system in response to the one or more characteristics of the program instructions awaiting issue.

Operation parameter control based upon queued instruction characteristics

A processor core includes a front end, and first and second back ends, the front end including a fetch engine configured to retrieve the sequence of data processing instructions for both the first back end and the second back end from a memory, and the first and second back ends are each configured to execute the sequence of program instructions. The core operates in a first mode in which the first back end is active and receives the sequence of data processing instructions from the fetch engine and the second back end is inactive, and a second mode in which the first back end is inactive and the second back end is active and receives the sequence of data processing instructions from the fetch engine, where the cycles-per-instruction rate is lower and energy consumption is higher for the first mode than the second mode.

Heterogeneity within a processor core

Disclosed is configuration memory access technology in a processor with a reconfigurable architecture. The processor with the reconfigurable architecture includes an array of processing elements (PEs), a configuration memory and a token network. The configuration memory stores configuration data associated with controlling data flow of the respective PEs. The token network reads the configuration data from the configuration memory, estimates data flow of the PEs from the read configuration data, reads required configuration data from the configuration memory based on the estimated data flow, and supplies the required configuration data to corresponding PEs. By reducing configuration memory access frequency through a token network, power consumption may be reduced.

Processor with reconfigurable architecture including a token network simulating processing of processing elements

Cooperative program code transformation includes receiving a transformation hint request, obtaining a suitable transformation hint, and providing the suitable transformation hint such that it is used to transform at least a portion of the program code and generate optimized code.

Cooperative program code transformation

An apparatus and method capable of reducing idle resources in a multicore device and improving the use of available resources in the multicore device are provided. The apparatus includes a static scheduling unit configured to generate one or more task groups, and to allocate the task groups to virtual cores by dividing or combining the tasks included in the task groups based on the execution time estimates of the task groups. The apparatus also includes a dynamic scheduling unit configured to map the virtual cores to physical cores.

Compiling apparatus and method of a multicore device

A data processing system is provided having a processor and analysing circuitry for identifying a SIMD instruction associated with a first SIMD instruction set and replacing it by a functionally-equivalent scalar representation and marking that functionally-equivalent scalar representation. The marked functionally-equivalent scalar representation is dynamically translated using translation circuitry upon execution of the program to generate one or more corresponding translated instructions corresponding to a instruction set architecture different from the first SIMD architecture corresponding to the identified SIMD instruction.

Growing community of inventors

Ann Arbor, MI, United States of America

Scott Mahlke