United Technologies Corporation

Johns Hopkins University

Aeroflex Colorado Springs Inc.

Utmc Microelectronic Systems Inc.

Aeroflex Utmc Microelectronics, Inc.

Scott M Tyson

Richard L Woodruff

Richard Y Kwor

David B Kerwin

John Chaffee

Gary M Wodek

Leonard L Levenson

Leonard L Levenson, Deceased

A method and apparatus for circumventing jamming of receivers for a global positioning system (GPS) include determining that a receiver is being jammed by a jamming signal not originating from the GPS. A first signal is transmitted from a portable unit including the receiver to a component of a second positioning system that is different from the GPS. A second signal is received from the second positioning system. The second signal includes data that indicates a position for the portable unit determined in the second positioning system based at least in part on the first signal.

Techniques for circumventing jamming of global positioning system receivers

A method for manufacturing a radiation hardened semiconductor device, having defined active region and isolation region. The isolation region containing an isolation material and active region containing a transition region between active and isolation region, sometimes denoted a bird's beak region. Wherein the transition region is implanted with germanium and boron, to prevent formation of leakage paths between active devices, or within an active device. The implanted area can be further limited to that area of the transition region that is adapted to be covered by a gate material, such as polysilicon.

Radiation hardened semiconductor device

A uniform film of sapphire and tungsten is deposited onto a surface of a substrate using the ionized cluster beam ('ICB') apparatus. During ICB deposition, a tungsten crucible containing sapphire is heated until a vapor of sapphire and tungsten is formed. The tungsten crucible is heated to form a tungsten vapor, which causes the crucible material to mix with the sapphire, thereby forming a vapor mixture of sapphire and tungsten. The vapor is ejected through a small nozzle into a vacuum region. The resulting adiabatic expansion of the vapor promotes formation of atomic clusters. Some of the clusters are ionized, and electrons are stripped off the clusters. The clusters are accelerated toward the substrate, which is also within the vacuum region. The clusters impact the surface of the substrate, where they are deposited to form the uniform sapphire/tungsten film. The film is deposited in an sapphire (aluminum oxide)/tungsten ratio of 2:1. The film has a relatively high index of refraction of approximately 2.2, thereby rendering it useful as an optical coating (specifically, an electrochromic material). The film may also be used as a resistive or thermally conductive material.

ICB method of forming high refractive index films

A method is disclosed for forming a buried contact within an integrated circuit ('IC'). Initially, a gate oxide layer is deposited onto a surface of a silicon substrate. A first polysilicon layer is deposited onto the gate oxide layer using an ionized cluster beam ('ICB') technique. The first polysilicon layer and the gate oxide layer are patterned and etched at predetermined locations, exposing the underlying silicon substrate surface at these locations. A small amount of undesirable native oxide grows on the exposed substrate surface. This oxide represents an unwanted impedance, which degrades IC device performance. The ICB machine is then used to deposit a second layer of polysilicon on the silicon substrate, including over the oxide layer regions and over the exposed silicon substrate surface at the predetermined locations. This second polysilicon deposition step breaks up and removes the unwanted native oxide from the silicon substrate.

Method of eliminating buried contact resistance in integrated circuits

An H-transistor, fabricated in a silicon-on-insulator ('SOI') substrate, includes opposing source and drain terminals or regions flanking a centrally-located body node or well. Above the body node or well is formed the H-shaped gate terminal of the transistor. One or more shunt body contacts or ties bisect the source terminal and connect the source terminal of the transistor to the underlying body node. In this way, the body node or well is no longer electrically 'floating', but, instead, is connected to the fixed ground potential of the source terminal of the transistor.

SOI combination body tie

Sapphire, a highly stable oxide of aluminum having the chemical formula of Al.sub.2 O.sub.3, is placed in a crucible. The crucible is heated to vaporize the sapphire therein. The sapphire vapor is ejected through a nozzle in the crucible and into a region having a vacuum pressure of approximately 10.sup.-5 Torr or less. As the vapor leaves the crucible through the nozzle, atom aggregates or clusters are formed through a supercooled phenomenon due to adiabatic expansion. The vacuum region has disposed therein a substrate of silicon. The sapphire vapor is accelerated towards the substrate where it deposits on a surface of the substrate in a uniformly distributed thin layer.

Ionized cluster beam deposition of sapphire and silicon layers

Sapphire, a highly stable oxide of aluminum having the chemical formula of Al.sub.2 O.sub.3, is placed in a crucible. The crucible is heated to vaporize the sapphire therein. The sapphire vapor is ejected through a nozzle in the crucible and into a region having a vacuum pressure of approximately 10.sup.-5 Torr or less. As the vapor leaves the crucible through the nozzle, atom aggregates or clusters are formed through a supercooled phenomenon due to adiabatic expansion. The vacuum region has disposed therein a substrate comprised of one of various materials, including metals, oxides or silicon. The sapphire vapor is accelerated towards the substrate where it deposits on a surface of the substrate in a uniformly distributed thin layer.

Ionized cluster beam deposition of sapphire

Two preferred embodiments for an alternative body contact are disclosed for fully-depleted silicon-on-insulator transistors. In one preferred embodiment, body contact is made by extending the mesa ends of the body ties down to, and merging them with, mesa regions of an nFET source and using self-aligned silicide (commonly known as salicide) to make a connection to an underlying nFET well. In this first embodiment, the mesas of the body ties merge with the mesa of the source and salicide is used to short out these regions. In another preferred embodiment, body contact is made by extending the mesa ends of the body ties down to the nFET source; however, the mesas are not merged. In this second embodiment, metal routing, which is commonly used to electrically connect circuit elements, is extended to connect to the mesa regions of the body ties. In both embodiments, the body ties are active until the onset of full depletion; however, at the onset of full depletion, the body ties are electrically severed.

Alternative body contact for fully-depleted silicon-on-insulator

An integrated circuit has a silicon mesa disposed on a substrate and a field insulator structure in proximity to the mesa and having an opening over a top mesa surface. The opening, which exposes sidewalls in the structure, is positioned with respect to the mesa and has dimensions such that the structure is disposed to overlap a region of the mesa along an outer mesa periphery. A layer of polysilicon extends along a top surface of the structure and into the opening and adjacent to the mesa top surface. An insulator is disposed between the poly layer and the mesa top surface, the insulator having a layer of thermal gate oxide disposed adjacent to the poly layer and having a layer of pyrogenic oxide disposed between the thermal gate oxide layer and the mesa top surface.

Field oxide termination and gate oxide

A method of treating the sidewalls of a transistor site aperture to form a gate insulator and increase the resistivity of the aperture sidewalls simultaneously combines an initial thin layer of thermal oxide with a thicker layer of pyrogenic oxide and a final layer of thermal oxide.

Field oxide termination and gate oxide formation

An SOI circuit includes a set of buried body ties that provide ohmic contact to the otherwise floating transistor bodies disposed on an insulating layer and both provide a path for holes generated by impact ionization and also act as a potential shield between the substrate potential and the transistor sources. The same fabrication technique provides a buried interconnect layer between transistors that can be employed as a mask programmable local interconnect in an ASIC such as a gate array. The process provides for independent control of differential mesa thickness and buried body tie thickness, so that fully and partially depleted transistors can be fabricated simultaneously and placed on appropriate mesas without affecting the body ties.

Method of making SOI circuit with buried connectors

A silicon on insulator transistor employs a thick field insulator overlapping silicon mesas, the overlap area beneath the interface between the transistor gate and the sidewall being doped to increase the threshold for parasitic transistors above that of the transistor.

Growing community of inventors

Colorado Springs, CO, United States of America

Scott M Tyson