Intel Corporation

Scott M Rider

David M Lee

Devdatta P Kulkarni

Frank E LeClerg

John Cruz Mejia

DeWitt Ong

Karen Navarro Castillo

Georges Manuel Faure Vaquero

Kenneth W Privitt

Technologies for dynamic cooling include a computing device having a multi-chip package including multiple dies and a cold plate coupled to the multi-chip package. Micro nozzle valves are coupled to fluid passage zones of the cold plate positioned adjacent to the dies, and are configured to control fluid flow into the fluid passage zones. The computing device reads a predetermined die junction temperature for each die, determines a current die junction temperature for each die, compares the predetermined die junction temperature to the current die junction temperature for each die, and determines a fluid flow rate for each die based on that comparison. The computing device controls the micro nozzle valves adjacent to each die based on the respective fluid flow rate. The dies may include processor cores, field-programmable gate arrays, memory devices, or other computer chips. Other embodiments are described and claimed.

Technologies for dynamic cooling in a multi-chip package with programmable impingement valves

Embodiments herein relate to multi-phase voltage regulator power phase duty cycle control in computer add-in cards. A computer add-in card may include a card body, a first power connector disposed on the card body, a second power connector, one or more multi-phase voltage regulators coupled with one or more of the first power connector and the second power connector, and a processor coupled with the one or more multi-phase voltage regulators, where the processor is to generate one or more power control signals and one or more of the one or more multi-phase voltage regulators is to adjust a duty cycle of one or more power phases in response to the one or more power control signals. In some embodiments, the power control signals may be serial voltage identification signals or may be provided over an inter-integrated circuit bus. Other embodiments may be described and/or claimed.

Voltage regulator phase duty cycle control apparatus and method

Aspects of the embodiments are directed to propagating an in-band hot reset through an add-in card compliant with a peripheral component interconnect express (PCIe) protocol. A host system can transmit an in-band hot reset to the add-in card across a link compliant with the PCIe protocol. A non-transparent bridge (NTB) on the add-in card can receive the in-band hot reset and reset configuration registers on the NTB. A system management controller can poll the NTB register values to determine that the polled configuration registers are different from expected values stored on an electrically erasable programmable random access memory (EEPROM). The SMC can signal a warm reset to a peripheral component based on the determination that the polled configuration register value is different from the expected register value.

Method, apparatus, and system for propagating PCIe hot reset across a non-transparent bridge on a PCIe add-in card

The disclosure describes a system including a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations over an interconnect to a second computer system. A second computer system includes a second memory controller and a second inter-computer transfer interface to receive the information about the write operations over an interconnect, wherein the write operations are duplicated through the second memory controller. In other embodiments, a system includes a first computer system including a first memory controller and a first inter-computer transfer interface to send information about write operations of the first computer system during a lockstep operation. Still other embodiments are described.

Multiple computer system processing write data outside of checkpointing

Example embodiments of an apparatus to reduce power consumed by a processor include a timing signal block configured to be coupled to measure the magnitude of an alternating current voltage signal supplied to a processor and to assert a timing signal when the magnitude of the alternating current voltage signal is about equal to zero volts and a throttling block configured to be coupled to the processor, to receive the timing signal and to assert a throttling signal that causes processor speed to be reduced so that processor power consumption is reduced in phase with the alternating current voltage signal and harmonic distortion of a current waveform supplied to the processor is reduced.

Platform power management for building wide control of power factor and harmonics

The present disclosure relates to resource management of memory using information regarding the physical state of the memory device(s), and, more specifically, to attempting to reduce the heat dissipation of a memory device by managing the contents of the memory device.

Thermal memory control

Briefly, in accordance with one embodiment of the invention, a method of transmitting coded data signals over a bus having a limited bandwidth includes: transmitting a first edge of a data pulse and transmitting a second edge of the data pulse. The time period between the transmitted first edge and the transmitted second edge approximates one of a set of different predetermined time periods. Selected different predetermined time periods of the set of different predetermined time periods respectively correspond to unique pluralities of binary digital signals. Briefly, in accordance with another embodiment of the invention, a system comprises a first device, a second device and a bandlimited bus coupling the first device with the second device. At least one of the devices includes the capability to code data signals for transfer over the bus and at least the other device includes the capability to decode the data signals. The data signals are coded so that selected different durations between pairs of successive data signal edges respectively correspond to unique pluralities of binary digital signals. Other embodiments include: a device including the capability to code data signals for transfer over a bandlimited bus; and a method, system, and device to decode data signals transmitted over a bandlimited bus.

System and method for transmitting coded data signals over a bandlimited

A technique of modifying a ROM mask to prevent external access of internal memory of an integrated circuit device. Patterns in the ROM mask are altered to permit implantation of components of a driver circuit such that these driver circuits are disabled. Disabling of the driver circuit prevents control signals from permitting external access of internal memory, therein allowing copy protection of the contents of the internal memory.

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Beaverton, OR, United States of America

Scott M Rider