Sun Microsystems, Inc.

Oracle America, Inc.

Scott M Fairbanks

Ivan E Sutherland

Robert J Drost

Josephus Ebergen

Charles E Molnar

Robert J Proebsting

Ronald Ho

Alex Chow

William Stuart Coates

David Money Harris

Charles E Molnar, Deceased

Arlene Proebsting, Legal Representative

Donna A Molnar

Arlene Proebsting

A method for calibrating an offset voltage of an amplifier used to amplify capacitively coupled communication signals is described. During this process, a common voltage is applied to one or more inputs to the amplifier. Next, an output of the amplifier is iteratively, measured, and charge is applied to the one or more inputs until the offset voltage is less than a pre-determined value. Note that applying the charge may involve applying a sequence of one or more charge pulses.

Offset cancellation in a capacitively coupled amplifier

A repeater circuit configured to duplicate or otherwise coordinate signal transitions between state conductors, such as for use in asynchronous communication systems. The repeater circuit may include a state node or other feature to facilitate enforcing or otherwise ordering transitioning of the state conductors.

Repeater circuit

A system of protecting a proximity communication system against electrostatic discharge (ESD). The proximity communication system includes two chips, each having an array of electrical pads at its surface and covered by a thin dielectric layer such that capacitive coupling circuits are formed between the chips when they are joined together. In at least one of the chips, an additional protection pad is formed away from the array, and heavy protection circuitry is connected to it. Its surface is exposed through the dielectric surface over it such that, when an ESD aggressor approaches, the discharge occurs to the protection pad.

Protection for proximity electronics against electrostatic discharge

Embodiments of the present invention provide a system for transferring data between a receiver chip and a transmitter chip. The system includes a set of data path circuits in the transmitter chip and a set of data path circuits in the receiver chip coupled to a shared data channel. In addition, the system includes a set of asynchronous control circuits for controlling corresponding data path circuits in the transmitter chip and receiver chip. Upon detecting the transition of a control signal for an asynchronous control circuit in the transmitter chip, the asynchronous control circuit is configured to enable a transfer of data from the corresponding data path circuit in the transmitter chip across the data channel to a corresponding data path circuit in the receiver chip, and generate a control signal to cause a next asynchronous control circuit to commence the transfer of a data signal.

Communicating signals between semiconductor chips using round-robin-coupled micropipelines

A booster circuit for reducing the nominal latency of a logic gate. The booster circuit includes a charge sharing mechanism to transfer a stored charge to the output of the logic gate in response to a logic state transition on the input of the logic gate. The transfer of stored charge also reduces the charge drawn from the supply during the output transition.

Booster circuits for reducing latency

An implicitly pulsed dual edge triggered pulsed latch. The implicitly pulsed latch includes an overlapping clock generator and a transparency circuit designed to cause a transparent latch circuit to become transparent on each edge of a clock signal. A logic value on the input node of the latch is transferred to the output node of the latch in response to each clock edge transition. An explicitly pulsed dual edge triggered pulsed latch including a pulse generator and a transparent latch circuit. The explicitly pulsed latch includes a symmetrical pulse generator designed to cause the latch circuit to pass a logic value from the input node of the latch to the output node of the latch in response to a pulse on the clock node.

Dual edge triggered flip flops

A duty cycle bounding circuit for restoring the unbounded duty cycle of a periodic signal such as a forwarded clock signal. The duty cycle bounding circuit comprises a state holding logic element, such as a C-element, and a delay line. The delay line feeds back an inverted version of the output of the state holding logic element to an input of the state holding logic element. The periodic signal is applied to another input of the state holding logic element.

Bounding a duty cycle using a C-element

An inverse toggle circuit includes a pair of input connections for receiving each of four possible input signal combinations in a sequential rotational manner. Each of four data paths are defined to be exercised in accordance with a respective input signal combination. A first output connection is controlled by first and third data paths. A second output connection is controlled by second and fourth data paths. Each data path is defined such that a currently exercised data path generates an output signal having an asserted state on the output connection that is controlled by the currently exercised data path. The currently exercised data path is also defined to cause a next data path in the sequence to generate an output signal having a non-asserted state on the output connection that is controlled by the next data path.

Multi-stage inverse toggle

A bifurcation circuit uses dynamic asP* protocol. to exchange data among three or more FIFOs. Each FIFO contains a plurality of places containing data and a plurality of paths that exchange data between neighboring places. The bifurcator circuit generally comprises a control FIFO, two subordinate FIFOs and a bifurcation path coupled to all three FIFOs. The bifurcator circuit further comprises a chain of data latches coupled to all three FIFOs at the bifurcation path. A data value carried in the control FIFO determines which of the subordinate FIFOs exchanges data with the control FIFO. Each place in the FIFOs contains a set reset flip-flop in which the state of each place is held by a single wire and stabilized by a keeper. A single transistor sets or resets the state of the place. The pulse that changes the state of the control flip-flops also makes the data latches momentarily transparent. The bifurcator circuit is generally capable of a branch or join operations. Alternatively, the bifurcation circuit may be implemented as a dedicated branch or join circuit. The circuits exhibit simple design, low power consumption low transistor count and easy integration into existing applications.

Asynchronous pulse bifurcator circuit with a bifurcation path coupled to control fifo and first and second subordinate fifo

A one-hot Muller C-element, wherein an event received on each of a plurality of inputs results in an event being output, can be implemented with complementary inputs and a true transistor pair comprising one transistor having a gate coupled to a first true input and another transistor having a gate coupled to a second true input; a true arm comprising the true transistor pair, coupled in series between a complement output and ground, and a true pull-up transistor, coupled between the complement output and a source; a true arm pull-up logic gate, coupled at its inputs to complement input wires of the one-hot Muller C-element and coupled at its output to a gate of the true pull-up transistor; a complement transistor pair comprising one transistor having a gate coupled to a first complement input and another transistor having a gate coupled to a second complement input; a complement arm comprising the complement transistor pair, coupled in series between a true output and ground, and a complement pull-up transistor, coupled between the true output and the source; and a complement arm pull-up logic gate, coupled at its inputs to true input wires of the one-hot Muller C-element and coupled at its output to a gate of the complement pull-up transistor.

One-hot Muller C-elements and circuits using one-hot Muller C-elements

A latching data system includes a memory element that is configured to store a data value. A latch input is coupled to the memory element, so that changes in the latch input change the data value stored in the memory element without waiting for an assertion of a clock signal. The system also includes a driver circuit that is configured to drive the data value stored in the memory element onto a latch output. The system additionally includes a clocking circuit that is configured to cause the driver circuit to drive the data value stored in the memory element onto the latch output in response to an assertion of the clock signal.

Method and apparatus for latching data within a digital system

One embodiment of the present invention provides a system for asynchronously controlling state information within a circuit. This system includes a first conductor that carries a voltage indicating a state of the circuit, as well as a first drive circuit coupled to the first conductor that is configured to drive the first conductor to a first voltage level to indicate a first state. The system also includes a second drive circuit coupled to the first conductor that is configured to drive the first conductor to a second voltage level to indicate a second state. The system additionally includes a condition input that indicates a condition. The system is configured so that the first drive circuit drives the first conductor to the first voltage level based upon the condition indicated by the condition input. In one embodiment of the present invention, the first drive circuit is additionally configured to drive the first conductor to the first voltage level based upon the state indicated by the voltage carried on the first conductor. In one embodiment of the present invention, the system additionally includes a keeper circuit coupled to the first conductor that is configured to hold the voltage on the first conductor at a stable value, unless the voltage is changed by a drive circuit. In one embodiment of the present invention, the system additionally includes a pulse generation circuit coupled to the first drive circuit, wherein the pulse generation circuit is configured to cause the first drive circuit to drive the first conductor to the first voltage level using a pulse of limited duration.

Method and apparatus for asynchronously controlling state information within a circuit

One embodiment of the present invention provides a system that generates a clock signal within an integrated circuit. This system includes four clocking elements organized into a ring, wherein each clocking element includes at least one input and at least one output, and wherein a signal at an input is complemented at a corresponding output. These clocking elements are spatially distributed throughout the integrated circuit, so that each clocking element provides the clock signal to a different region of the integrated circuit. These clocking elements are also coupled together though a plurality of interconnections, so that each output of each clocking element is coupled to at least one input of a neighboring clocking element. Furthermore, a given signal is inverted an odd number of times in traversing a closed path beginning and ending at any output of any of the four clocking elements and passing through a neighboring clocking element. In one embodiment of the present invention, each of the four clocking elements contains, a first node and a second node that are coupled together by a keeper circuit. Each clocking element also includes a first pair of inverters, each of which has an output coupled to the first node, and a second pair of inverters, each of which has an output coupled to the second node.

Method and apparatus for generating and distributing a clock signal

One embodiment of the present invention provides a system for controlling asynchronous data transfers within a circuit. This system operates by monitoring a first voltage level on a first conductor that specifies whether a first stage of the circuit contains data. The system also monitors a second voltage level on a second conductor that specifies whether a second stage of the circuit contains data. Upon detecting that the first voltage level indicates that first stage contains data to be transmitted to the second stage, and that the second voltage level indicates that the second stage does not contain data, and is therefore available to receive data from the first stage, the system transfers the data from the first stage to the second stage. This is accomplished by generating a second stage latch signal to latch data into the second stage from the first stage. It also involves changing the first voltage level to indicate that the first stage no longer contains data, and changing the second voltage level to indicate that the second stage contains data.

Asynchronously controlling data transfers within a circuit

A Muller C-element comprises two stages. The first stage consists of a NAND and a NOR gate, each driven by all of the inputs to the Muller C-element. In the second stage, the outputs of the two gates are used separately to switch on and off two output transistors, which drive the output of the Muller C-element A keeper flip flop serves to retain the output value between changes. Because current from each gate is applied only to one output transistor, delay is reduced. Furthermore, an unneeded output transistor is switched off as soon as logically possible, often during the otherwise unused interval while the input values differ, which reduces both delay and crossover current. In a preferred embodiment, the NAND and NOR gates each comprise a set of series transistors and a set of parallel transistors. The parallel transistors in these gates work together to change the output value when all inputs are changing simultaneously, thereby allowing the use of parallel transistors having widths narrower than those normally employed in NAND and NOR gates. Use of smaller transistors renders the inputs easier to drive, improving the speed of the circuit.

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Mountain View, CA, United States of America

Scott M Fairbanks