Synopsys, Inc.

Other

Scott Lawrence Howe

Dino Anthony Toffolon

Cameron Lacy

Euhan Chong

Chris Ouslis

A mixed signal integrated circuit includes a signal source to inject a test signal into the signal path of the mixed signal integrated circuit, a feedback loop and a signal comparator for determining characteristics of a resulting signal. Conveniently, the test signal may be a digital signal injected upstream of a digital to analog converter (DAC). By connecting the output to the input, the entirety of the signal path and the majority of the integrated circuit may be tested. The signal may be condition or manipulated in the feedback loop. By incorporating test signal generation and measurement into the mixed signal integrated circuit, the cost of test equipment and the test duration for each device under test may be reduced.

Mixed signal integrated circuit, with built in self test and method

A high current drive bandgap based voltage regulator for providing a reference voltage at a an output voltage at a designed output voltage value. The high current drive bandgap based voltage regulator includes a high current drive output transistor, a feedback network, an output terminal and an operational amplifier. The feedback network is coupled between the output of the transistor and the input of the transistor. The operational amplifier is in the feedback network and has at least two operational amplifier input terminals and an operational amplifier output terminal. The operational amplifier output terminal is coupled to the transistor input terminal, and the operational input terminals are coupled to the transistor output terminal. The output terminal of the high current drive bandgap based voltage regulator is coupled to the output of the high current drive transistor. The high current drive bandgap based voltage regulator is operable to provide a current of at least 100 &#x3bc;A to the output terminal while maintaining the output voltage at the output terminal at a value substantially equal to the designed output voltage value.

High current drive bandgap based voltage regulator

A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D&#x2212; signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45&#x3a9;&#xb1;10%) in the USB transceiver.

USB 2.0 HS voltage-mode transmitter with tuned termination resistance

A high-speed universal serial bus (USB) transceiver includes a voltage-mode architecture for generating a USB signal. The voltage mode architecture reduces power consumption by reducing the current requirements for high-speed USB communications. The USB transceiver can include a reference voltage generator, a resistive element, and a switching element for completing and breaking a circuit including the reference voltage generator, the resistive element, and a data pin of a USB port to generate half of the differential USB signal (e.g., the D+ signal). A similar circuit can be used to generate the other half of the differential USB signal (i.e., the D&#x2212; signal). The resistive element can be a set of parallel resistors in the transceiver, with the set of parallel resistors being specifically selected from a larger population of resistors to provide the specified resistance (45 &#x3a9;&#xb1;10%) in the USB transceiver.

A Universal Serial Bus (USB) 2.0 transceiver includes a legacy full speed and low speed (FS/LS) USB driver that includes multiple output stages. The multiple output stages are connected in parallel to an output terminal. By sequentially providing the USB data to the multiple output stages, the USB signal at the output terminal will transition between logic states in an incremental fashion as the multiple output stages sequentially switch their individual output states. Consequently, the rise/fall time for the legacy FS/LS USB driver is controlled not by the strength of the inverter transistors in the output stages, but rather by the number of stages and the time interval between application of the USB data to each stage. Therefore, by selecting an appropriate number of output stages and an appropriate timing interval, accurate control over full speed and low speed USB signal rise/fall times can be provided.

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Campbellville, Canada

Scott Lawrence Howe