Honeywell International Inc.

Honeywell G.m.b.h.

Scott L Gray

Nicholas J Wilt

Steven R Thompson

Gary A Walker

Mitch Fletcher

Kevin Stover

Michael W Bartels

Neil L Sampson

A self-checking network is provided, comprising a first command processor configured to execute a performance function and a second command processor configured to execute the performance function, coupled to the first command processor. The self-checking network also comprises a first monitor processor configured to execute a monitor function that is coupled to the first command processor and a second monitor processor configured to execute the monitor function that is coupled to the second command processor. The first and second command processors compare outputs, the first and second monitor processors compare outputs, and the first monitor processor determines whether an output of the first command processor exceeds a first selected limit.

Integrated dissimilar high integrity processing

A multi-core processor chip comprises at least one shared cache having a plurality of ports and a plurality of address spaces and a plurality of processor cores. Each processor core is coupled to one of the plurality of ports such that each processor core is able to access the at least one shared cache simultaneously with another of the plurality of processor cores. Each processor core is assigned one of a unique application or a unique application task and the multi-core processor is operable to execute a partitioning operating system that temporally and spatially isolates each unique application and each unique application task such that each of the plurality of processor cores does not attempt to write to the same address space of the at least one shared cache at the same time as another of the plurality of processor cores.

Multi-core processing cache image management

Methods and apparatus are provided for verifying the integrity of a signal transmitted across a multiple rail data bus. The method and apparatus provide for independently processing a signal by a first processor and a second processor, the first and second processors being connected in parallel thereby generating a first processed signal and a second processed signal. Each of the processed signals is split into a first component sequence and a second component sequence, the first component sequences being different from the second component sequences. It is then determined that the first component sequences are not identical and that the second component sequences are not identical. If either of the first component sequences is not identical, or if either of the second component sequences is not identical, then an error signal is transmitted to a receiving device via a first or second rail of the bus.

High integrity data bus fault detection using multiple signal components

A method for refreshing memory is provided. The method comprises determining when a first memory of a plurality of memories is not being accessed and sending a refresh opportunity command from a master refresh controller to one of a plurality of local refresh controllers when the first memory is not being accessed, wherein the one of a plurality of local refresh controllers controls only the first memory. The method further comprises determining when the first memory needs refreshing and refreshing the first memory.

Reducing power consumption for dynamic memories using distributed refresh control

Systems and methods for improved multiple-port memory are provided. In one embodiment, a processing system comprises: at least one processing core; a peripheral bus; and a memory for storing digital data, the memory divided into a first and a second partition of memory segments. The memory includes a first port coupled to the peripheral bus providing read access and write access only to the first partition, wherein the first partition stores peripheral data associated with one or more peripheral components coupled to the peripheral bus; a second port coupled to the at least one processor providing read-only access to only the second partition, wherein the second partition stores executable code for the at least one processing core; and a third port coupled to the at least one processor providing read access and write access to the entire first partition and the second partition.

Multiple-port memory systems and methods

Methods and systems are disclosed for the detection and correction of memory errors using code words with a quantity, divisible by 4, of data bits, with an equal quantity of check bits, and having the check bits and data bits interleaved. Upon execution of a memory write instruction, a processor may send a memory word to a check bit generator that generates the check bits before the code word is written to a memory unit. Upon a signal from the processor that a memory read is requested, the memory unit may send a stored code word to a syndrome bit generator to generate a syndrome vector. The syndrome vector may then be sent to a correction bit generator and an uncorrectable error detector. These units may send corrected bits and an uncorrectable error signal, respectively, to the processor.

High speed memory error detection and correction using interleaved (8,4) LBCs

Systems and methods for bounded minimal latency for network resources without synchronization are provided. In one embodiment, a method for managing data traffic between nodes in an asynchronous network comprises: receiving a data request message at a first port of network switch; storing information about the data request message in a memory at the network switch; forwarding the data request message to a producer node; receiving a data message at a second port of the network switch; determining whether the data message is responsive to the data request message; when the data message is responsive, forwarding the data message from the network switch; and when the data message is not responsive, blocking the data message from being forwarded from the network.

Bounded minimal latency for network resources without synchronization

A communication network is provided. The network includes a least one switch and a plurality of ports. Each port is in communication with the at least one switch. At least one of the ports is configured to introduce a time delay after each transmission of a frame based at least in part on a maximum transmission rate of the at least one port and its allocated transmission rate.

Port rate smoothing in an avionics network

A method for initializing a chain of non-initialized data collectors is disclosed. The chain of non-initialized data collectors are coupled to a controller. In a first step communication between the controller and each data collector in the chain of non-initialized collectors is disabled, except for an active non-initialized data collector, The active non-initialized collector is coupled to the controller and any remaining non-initialized data collectors. Next, the active non-initialized data collector is initialized by assigning an identification number to the active non-initialized data collectors. The active non-initialized collector becomes an initialized data collector. Then, communication is restored between the initialized data collector and a next active non-initialized data collector in the chain of non-initialized data collectors. The method repeats until all non-initialized data collectors are initialized.

Method for sensor initialization in a structural health management system

Methods and system for facilitating a computing platform to recover quickly from transient multi-bit data failures within a run-time data memory array in a manner that is transparent to software applications executing on the computing platform. A fault-tolerant digital computing system is provided for that utilizes parallel processing lanes in a lockstep architecture. Each processing lane includes error detectors that are configured to detect multi-bit data errors in each processing lane's memory arrays. Upon detection of a multi-bit data failure, an interrupt is generated wherein control logic software responds to the interrupt and corrects the data errors in the memory array of each processing lane.

High integrity recovery from multi-bit data failures

A digital computing system includes a first and second processor clocked for locked step operation. A shared memory stores a linear block codeword across a plurality of byte-wide memory devices. The codeword includes a first dataword and a second dataword. Each of the first and second datawords includes an equal plurality of databits and each includes an equal plurality of checkbits associated therewith. First error detection and correction logic connected to the first processor receives the first dataword and checkbits associated therewith of the codeword addressed by the first processor and a second dataword and checkbits associated therewith of the codeword addressed by the second processor. First error detection and correction logic detects and/or corrects errors in the codeword. Second error detection and correction logic connected to the second processor receives the second dataword and checkbits associated therewith of the codeword addressed by the second processor and the first dataword and checkbits associated therewith of the codeword addressed by the first processor. The second error detection and correction logic detects and/or corrects errors in the codeword.

Error detection and correction for data stored across multiple byte-wide

A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.

Growing community of inventors

Glendale, AZ, United States of America

Scott L Gray