Texas Instruments Corporation

Scott Kelly Montgomery

Binghua Hu

Scott Robert Summerfelt

Alexei Sadovnikov

Byron Lovell Williams

Maxwell Walthour Lippitt, Iii

Yingsheng Tung

Betty S Mercer

Ming-Yeh Chuang

Asad Mahmood Haider

William C Loftin

James Wayne Klawinsky

Byron Lovell Willaims

An electronic device, e.g. an integrated circuit, includes a semiconductor substrate having a top surface and an area of the semiconductor substrate surrounded by inner and outer trench rings. The inner trench ring includes a first dielectric liner that extends from the substrate surface to a bottom of the inner trench ring, the first dielectric liner electrically isolating an interior region of the inner trench ring from the semiconductor substrate. The outer trench ring surrounds the inner trench ring and includes a second dielectric liner that extends from the substrate surface to a bottom of the outer trench ring. The second dielectric liner includes an opening at a bottom of the outer trench ring, the opening providing a path between an interior region of the outer trench ring and the semiconductor substrate.

Sinker to buried layer connection region for narrow deep trenches

A method of forming an IC includes forming a buried layer (BL) doped a second type in a substrate doped a first type. Deep trenches are etched including narrower inner trench rings and wider outer trench rings through to the BL. A first deep sinker implanting uses ions of the second type with a first dose, a first energy, and a first tilt angle. A second deep sinker implant uses ions of the second type with a second dose that&#x3c;the first dose, a second energy&#x3e;than the first energy, and a second tilt angle&#x3c;the first tilt angle. The outer trench rings outside and inner trench rings are dielectric lined. The dielectric lining is removed from a bottom of the outer trench rings. The outer trench rings are filled with an electrically conductive filler material that contacts the substrate and fills the inner trench rings.

A process for forming an integrated circuit with a dilution doped resistor with a resistance that may be tuned by partially blocking the implant used to dope the resistor. A process for forming an integrated circuit with a dilution doped polysilicon resistor by partially blocking the resistor dopant implant from a portion of the polysilicon resistor body.

Dilution doped integrated circuit resistors

An integrated circuit structure with a metal-to-metal capacitor and a metallic device such as a resistor, effuse, or local interconnect where the bottom plate of the capacitor and the metallic device are formed with the same material layers. A process for forming a metallic device along with a metal-to-metal capacitor with no additional manufacturing steps.

Integrated circuit structure with capacitor and resistor and method for forming

In a disclosed embodiment, a stacked capacitor () has bottom, middle and top metal electrode layers (A,B,C) interleaved with dielectric layers (A,B) conformally disposed within holes (A,B,C) in a protective overcoat or backend dielectric layer () over a top metal layer () of an integrated circuit (). A top electrode () contacts the top metal electrode layer (C). A bottom electrode () electrically couples an isolated part of the top metal electrode layer (C) through a bottom electrode via (A) to a first contact node (A) in the top metal layer () which is in contact with the bottom metal electrode layer (A). A middle electrode () electrically couples a part of the middle metal electrode layer (B) not covered by the top metal layer () through a middle electrode via (B) to a second contact node (B) in the top metal electrode layer (). The sidewalls of the top and middle electrode vias (A,B) are lined with insulating material to electrically isolate the metal electrode layer ends.

Multiple electrode layer backend stacked capacitor

An embodiment generally relates a method of forming capacitors. The method includes forming a plurality of holes within a protective overcoat or backend dielectric layer of an integrated circuit and depositing multiple layers of metal, each layer of metal electrically tied to an associated electrode. The method also includes alternately depositing multiple layers of dielectric between the multiple layers of metal and coupling a bottom layer of the multiple layers of metal to a contact node in a top metal layer of the integrated circuit.

Methods and devices for a high-k stacked capacitor

The present invention provides a diodethat includes a substratedoped with a first type dopant and a double implanted guard ringlocated within the substrate and doped with a second type dopant opposite the first type dopant and having a first doped profile regionand a second doped profile region. The present invention also includes a method of manufacturing this diode and an integrated circuit that utilizes this diodewithin a CMOS and bipolar transistor integrated circuit

Diode having a double implanted guard ring

An antifuse (42) is formed by forming a layer of titanium tungsten (34) overlying a portion of a first metal layer (28). The titanium tungsten layer (34) is oxidized to form a film of oxide (36) on its surface. Insulating regions (30) are formed adjacent the titanium tungsten layer (34) and overlying the first metal layer (28). A second metal layer (40) is formed overlying the titanium tungsten layer (34). Applying a break down voltage across the first and second metal layers (28), (40) will break down the oxide film (36), thereby causing a connection between the first and second metal layers (28), (40).

Growing community of inventors

Rowlett, TX, United States of America

Scott Kelly Montgomery