International Business Machines Corporation

Globalfoundries Inc.

Scott Keith Springer

Sungjae Lee

James Johnson

Lan Luo

Jonghae Kim

Siyuranga O Koswatta

Richard Andre Wachnik

Edward J Nowak

Richard Quimby Williams

Jean-Olivier Plouchart

Josef S Watts

Myung-Hee Na

Jean-Oliver Plouchart

Paul A Hyde

Rainer Thoma

Steven G Lovejoy

Sim Y Loo

Yanqing Deng

Todd G McKenzie

A semiconductor structure comprises one or more semiconductor devices, each of the semiconductor devices having two or more electrical connections; one or more first conductors connected to a first electrical connection on the semiconductor device, the first conductor comprising a first material having a positive Seebeck coefficient; and one or more second conductors connected to a second electrical connection on the semiconductor device, the second conductor comprising a second material having a negative Seebeck coefficient. The first conductor and the second conductor conduct electrical current through the semiconductor device and conduct heat away from the semiconductor device.

Integrated circuits with Peltier cooling provided by back-end wiring

Aspects of the present disclosure include a computer-implemented method for designing a temperature-compliant integrated circuit (IC). The method can include: calculating a thermal resistance of an IC layout, the IC layout having an area-dependent thermal conductance, a fin thermal conductance, and a gate thermal conductance each based on a device geometry of a plurality of transistors in the IC layout; calculating a self-heating temperature as directly proportional to the thermal resistance; comparing the self-heating temperature with a threshold temperature; in response to the self-heating temperature exceeding the threshold temperature, automatically modifying the device geometry of the IC layout to reduce at least one of the area term and the perimeter term, thereby reducing the self-heating temperature of the IC layout; and designing the temperature-compliant IC layout by repeating the calculating and automatically modifying steps until the self-heating temperature does not exceed the threshold temperature.

Temperature-compliant integrated circuits

Integrated circuits with peltier cooling provided by back-end wiring

Disclosed are embodiments of a method, system and program storage device for generating accurate performance targets for active semiconductor devices during technology node development in order to reduce the number of iterations required for model extraction and/or to improve model quality. In these embodiments, initial sets of performance targets for related semiconductor devices are generated, e.g., by making assumptions based on hardware measurements taken from semiconductor devices in prior technology nodes. Additional processes are then performed on the initial sets of performance targets prior to the modeling stage in order to detect and resolve any inconsistencies between the data in the sets. Specifically, plotting techniques are performed with respect to the performance targets. The results are analyzed to detect any inconsistencies indicating that the performance targets are inaccurate and adjustments are made to the performance targets in order to resolve those inconsistencies.

Method, system and program storage device for generating accurate performance targets for active semiconductor devices during new technology node development

A system and method for developing condensed netlists for sub-circuits within an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists rather than full netlists. An IC layout is segmented into a plurality of sub-circuits, each comprising a group of one or more of a given type of active devices connected to (i.e., sharing) the same electrical sub-circuit terminals through a similar resistive network (i.e. such that they are subjected to approximately the same overall combined parasitic resistances). Full netlists corresponding to the sub-circuits are extracted from the layout and condensed. Each condensed netlist accounts for performance variations (e.g., as a function of variations in operating power supply voltages, operating temperatures and, optionally, self-heating and/or stress) exhibited by the active devices and resistive network in a sub-circuit. The condensed netlists for the sub-circuits are then simulated over the full range of operating temperatures and full range of operating power supply voltages for the integrated circuit in order to generate a performance model for the integrated circuit.

System, method and program storage device for developing condensed netlists representative of groups of active devices in an integrated circuit and for modeling the performance of the integrated circuit based on the condensed netlists

Disclosed herein are embodiments of an automated, fast and efficient method of generating a customized compact model that represents a semiconductor device at the chip, wafer or multi-wafer level in a specific manufacturing environment. Specifically, measurement data is collected from a specific manufacturing environment and sorted by channel lengths. Then, an optimizer is used to generate customized modeling parameters based on the measurement data. The optimization processes is a multi-step process. First, a first set of modeling parameters is generated based on measurement data associated with a long channel length. Second, a second set of modeling parameters is generated based on the first set and on measurement data associated with a short channel length. Finally, the customized modeling parameters are generated based on both the first set and the second set. The customized modeling parameters are used to generate a customized compact device model representative of the specific manufacturing environment.

Efficient methodology for the accurate generation of customized compact model parameters from electrical test data

A fast FET, a method and system for designing the fast FET and a design structure of the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

High-performance FET device layout

A fast FET and a method and system for designing the fast FET. The method includes: selecting a reference design for a field effect transistor, the field effect transistor including a source, a drain, a channel between the source and drain, a gate electrode over the channel, at least one source contact to the source and at least one contact to the drain, the at least one source contact spaced a first distance from the gate electrode and the at least one drain contact spaced a second distance from the gate electrode; and adjusting the first distance and the second distance to maximize a performance parameter of the field effect transistor to create a fast design for the field effect transistor.

Growing community of inventors

Burlington, VT, United States of America

Scott Keith Springer