Western Digital Technologies, Inc.

University of California

Scott Kayser

Richard David Barndt

Majid Nemati Anaraki

Anthony Dwayne Weathers

Seyhan Karakulak

Jack K Wolf

Jun Tao

Aldo Giovanni Cometti

Niang-Chu Chen

Alexander Vardy

Paul Siegel

Eitan Yaakobi

The subject technology provides for scanning blocks of a flash memory device for erased pages. A first codeword read from a page of a block in a flash memory device is received and provided to a first decoder for decoding. In response to receiving a first success indicator from the first decoder indicating that the first codeword was successfully decoded, first decoded data is provided from the first decoder to a second decoder for verification of the first decoded data. In response to receiving a first failure indicator from the second decoder indicating that the first decoded data was not verified, the page of the block is identified as being in an erased state based on the first success indicator received from the first decoder and the first failure indicator received from the second decoder.

Method and system for identifying erased memory areas

A system for hierarchical variable code rate error correction coding may include at least one circuit that is configured to identify a row of a hierarchical portion of a generator matrix that corresponds to a determined code rate, determine a number of information bits to apply to the hierarchical portion based at least on the identified row, and apply the determined number of information bits to the identified row. The circuit may be further configured to apply an output of the identified row to a subsequent row of the hierarchical portion, when the hierarchical portion includes a subsequent row, and apply an output of a last row of the hierarchical portion to a base portion of the generator matrix. The circuit may be further configured to provide a codeword output by the base portion of the generator matrix.

Hierarchical variable code rate error correction coding

Method and system for scanning for erased flash memory pages

A device that provides for adaptive wear levelling includes at least one processor. The at least one processor utilizes sets of blocks of flash memory circuits for data storage operations, each set of blocks including a block from each flash memory circuit and at least some of the blocks being marked active for the data storage operations. The at least one processor monitors a quality metric of each block while the blocks marked active are utilized for data storage operations. The at least one processor determines when the quality metric of a block falls below a minimum level and marks the block as temporarily inactive, where the block is not utilized for the data storage operations while marked temporarily inactive. The at least one processor, when a criterion is satisfied, marks the block as active so that the block can again be utilized for the data storage operations.

Adaptive wear levelling

Multiple reads of memory cells of a flash memory device are initiated at different read levels to obtain raw data. For each different read level, multiple decoding operations are initiated to decode the raw data, each decoding operation using a different one of a plurality of sets of decoding information associated with the different read level. Decoding success rates are determined for one or more of the plurality of sets based on the one or more of the plurality of sets being used to successfully decode data and, for each different read level, an order of the plurality of sets is determined based on the determined success rates. A selected set of decoding information is selected for use in decoding raw data obtained from a read performed at a respective read level based on the respective read level and the set order of the plurality of sets for the respective read level.

Dynamic selection of soft decoding information

The invention provides a family of 2-write WOM-codes, preferred embodiments of which provide improved WOM-rates. Embodiments of the invention provide constructs for linear codes C having a 2-write WOM-code. Embodiments of the invention provide 2-write WOM-codes that improve the best known WOM-rates known to the present inventors at the time of filing with two writes. Preferred WOM-codes are proved to be capacity achieving when the parity check matrix of the linear code C is chosen uniformly at random. Preferred embodiments of the invention provide an electronic device utilizing an efficient coding scheme of WOM-codes with two write capability. The coding method is based on linear binary codes and allows the electronic device to write information to the memory twice before erasing it. This method can be applied for any kind of memory systems, and in particular for flash memories. The method is shown to outperform all well-known codes.

Efficient two write WOM codes, coding methods and devices

Growing community of inventors

San Diego, CA, United States of America

Scott Kayser