Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Scott K Pozder

Thomas Sachio Kobayashi

Jie-Hua Zhao

Edward Outlaw Travis, Jr

Robert E Jones

Kevin John Hess

Trent Uehling

Brett P Wilkerson

Ritwik Chatterjee

David G Wontor

Michelle F Rasco

Syed M Alam

Varughese Mathew

Byoung W Min

George R Leal

Robert Joseph Wenzel

Ruiqi Tian

Dean J Denning

Sam S Garcia

Vance H Adams

George F Carney

Lakshmi Narayan Ramanathan

Pak Leung

Addi B Mistry

Deborah A Hagen

Peng Su

Lynne M Michaelson

Stephen G Sheck

Harold A Downey

Rina Chowdhury

Jiming Zhang

Rebecca G Cole

Katie C Yu

Salih M Celik

Kartik Ananthanarayanan

A die-on-die assembly has a first die () and a second die (). The first die () has a first contact extension () and a peg () extending a first height above the first die. The second die () has a second contact extension () connected to the first contact extension and has a containing feature () extending a second height above the second die surrounding the peg. The peg extends past the containing feature. Because the peg extends past the containing feature, lateral movement between the first and second die can cause the peg to come in contact with and be constrained by the containing feature. The peg and containing feature are thus useful in constraining movement between the first and second die.

3-D semiconductor die structure with containing feature and method

A method of assembling an electronic device includes testing a first wafer of first die to identify the location of functional first die and dividing the first wafer into a set of panels, wherein a panel includes an M&#xd7;N array of first die. A panel is bonded to a panel site of a second wafer to form a panel stack wherein a panel site defines an M&#xd7;N array of second die in the second wafer. The panel stack is sawed into a devices comprising a first die bonded to a second die. Dividing the first wafer into panels may be done according statically or dynamically (to maximize the number of panels having a yield exceeding a specified threshold). Binning of the panels and panel sites according to functional die patterns may be performed to preferentially bond panels to panel sites of the same bin.

Fabrication of three dimensional integrated circuit employing multiple die panels

A bump shear test is disclosed for evaluating the mechanical integrity of low-k interconnect stacks in an integrated circuit which includes a die test structure () having a stiff structural component () positioned above and affixed to a conductive metal pad () formed in a last metal layer (). The die test structure () may also include a dedicated support structure () below the conductive metal pad which includes a predetermined pattern of metal lines formed in the interconnect layers (). After mounting the integrated circuit in a test device, a shear knife () is positioned for lateral movement to cause the shear knife to contact the stiff structural component (). Any damage to the die test structure caused by the lateral movement of the shear knife may be assessed to evaluate the mechanical integrity of the interconnect stack.

Mechanical integrity evaluation of low-k devices with bump shear

A method of forming an embedded device build-up package () includes forming a first plurality of features () over a packaging substrate (), wherein the first plurality of features () comprises a first feature and a second feature, forming at least a first crack arrest feature () in a first crack arrest available region (), wherein the first crack arrest available region is between the first feature and the second feature, forming a second plurality of features () over the first plurality of features () wherein the second plurality of features includes a third feature and a fourth feature, and forming at least a second crack arrest feature () in a second crack arrest available region (), wherein the second crack arrest feature () is between the third feature and the fourth feature, and the second crack arrest feature () is substantially orthogonal to the first crack arrest feature ().

Method of forming crack arrest features in embedded device build-up package and package thereof

A fuse () is formed overlying a passivation layer () and under a packaging material (). In one embodiment, a fuse () is blown before the packaging material () is formed. In some embodiments, the fuse () may be formed of metal (), a metal nitride () or a combination thereof.

Semiconductor device having a fuse and method of forming thereof

A method for forming a semiconductor device includes providing a first integrated circuit having a landing pad and attaching a second integrated circuit to the first integrated circuit using at least one bonding layer. The second integrated circuit has an inter-circuit trace, the inter-circuit trace has an inter-circuit trace opening. The method further includes forming an opening through the second integrated circuit, the opening extending through the inter-circuit trace opening, forming a selective barrier on exposed portions of the inter-circuit trace in the opening, extending the opening through the at least one bonding layer to the landing pad, and filling the opening with a conductive fill material. The selective barrier layer comprises at least one of cobalt or nickel, and the conductive fill material electrically connects the inter-circuit trace and the landing pad.

Barrier for use in 3-D integration of circuits

A reciprocal design symmetry allows stacked wafers or die on wafer to use identical designs or designs that vary only by a few layers (e.g. metal interconnect layers). Flipping or rotating one die or wafer allows the stacked die to have a reciprocal orientation with respect to each other which may be used to decrease the interconnect required between the vertically stacked die and or wafers. Flipping and/or rotating may also be used to improve heat dissipation when wafer and/or die are stacked. The stacked wafers or die may then be packaged.

Semiconductor stacked die/wafer configuration and packaging and method thereof

An integrated circuit has metal bumps on the top surface that create a potentially destructive stress on the underlying layers when the metal bumps are formed. Ensuring a minimum metal concentration in the underlying metal interconnect layers has been implemented to reduce the destructive effect. The minimum metal concentration is highest in the corners, next along the border not in the corner, and next is the interior. The regions in an interconnect layer generally under the metal bump require more concentration than adjacent regions not under a bump. Lesser concentration is required for the metal interconnect layers that are further from the surface of the integrated circuit. The desired metal concentration is achieved by first trying a relatively simple solution. If that is not effective, different approaches are attempted until the minimum concentration is reached or until the last approach has been attempted.

Die level metal density gradient for improved flip chip package reliability

A technique for alleviating the problems of defects caused by stress applied to bond pads () includes, prior to actually making an integrated circuit (), adding dummy metal lines () to interconnect layers () to increase the metal density of the interconnect layers. These problems are more likely when the interlayer dielectrics () between the interconnect layers are of a low-k material. A critical area or force area () around and under each bond pad defines an area in which a defect may occur due to a contact made to that bond pad. Any interconnect layer in such a critical area that has a metal density below a certain percentage can be the cause of a defect in the interconnect layers. Any interconnect layer that has a metal density below that percentage in the critical area has dummy metal lines added to it.

Integrated circuit having structural support for a flip-chip interconnect pad and method therefor

A composite bond pad that is resistant to external forces that may be applied during probing or packaging operations is presented. The composite bond pad includes a non-self-passivating conductive bond pad () that is formed over a semiconductor substrate (). A dielectric layer () is then formed over the conductive bond pad (). Portions of the dielectric layer () are removed such that the dielectric layer () becomes perforated and a portion of the conductive bond pad () is exposed. Remaining portions of the dielectric layer () form support structures () that overlie that bond pad. A self-passivating conductive capping layer () is then formed overlying the bond pad structure, where the perforations in the dielectric layer () allow for electrical contact between the capping layer () and the exposed portions of the underlying bond pad (). The support structures () provide a mechanical barrier that protects the interface between the capping layer () and the bond pad (). Additional mechanical robustness is achieved when the support structures () remain coupled to the unremoved portion of the dielectric layer (), as forces buffered by the support structures () are distributed across the dielectric layer () and not concentrated at the bond pad location.

Method for forming a bond pad interface

A semiconductor device is attached to a heat sink by glue that is both thermally conductive and magnetically permeable. The glue fills different features in the surface of the semiconductor device so that there is good coupling between the semiconductor device and the heat sink. The glue is filled with magnetic particles so that the glue is magnetically permeable. The semiconductor device is formed with the heat sink at the wafer level and then singulated after attachment of the heat sink with the glue.

Semiconductor device with magnetically permeable heat sink

An integrated circuit with a first plurality of transistors formed on a first wafer and second plurality of transistors formed on a second wafer. At least a substantial majority of the transistor of the first transistor are of a first conductivity type and at least a substantial majority of the transistors of the second plurality are of a second conductivity type. After wafers are bonded together, a portion of the second wafer is removed wherein the strain of the channels of the second plurality of transistors is more compressive than the strain of the channels of the first plurality of transistors.

Separately strained N-channel and P-channel transistors

A process for removing metal from a scribe area of a semiconductor wafer. The metal removed may include exposed metal in a saw path of the scribe area and the metal in a crack stop trench of the scribe area. In one example, copper is removed from the scribe area by wet etching the wafer. In one example, the wet etching process is performed after the removal of an exposed barrier adhesion layer on the wafer surface. Removal of the metal in the saw path may reduce the amount of metal buildup on a saw blade during singulation of the die areas of a wafer.

Growing community of inventors

Austin, TX, United States of America

Scott K Pozder