Scdevice LLC

Scott Joseph Alberhasky

Sudarsan Uppili

David Lee Snyder

Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

Vertical trench device configurations for radiation-environment applications

Vertical diodes are disclosed herein for radiation-environment applications. The diodes can be junction barrier Schottky (JBS) diodes. A disclosed vertical diode includes a first region with a first conductivity type, fingers with a second conductivity type and located in a top portion of the first region, at least one tap region with the first conductivity type formed in the fingers, and a metal layer located over and in contact with the first region and the fingers and forming a Schottky barrier with the first region. Another disclosed vertical diode includes a first region with a first conductivity type, fingers with a second conductivity type located in a top portion of the first region and having a well doping concentration, and a metal layer located over the first region and the fingers and forming a Schottky barrier with the first region.

Vertical diode configurations for radiation-environment applications

Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer in contact with the first mask, and implanting a shallow well region in the drift region using the first mask and the spacer. A disclosed FET includes a drift region, a shallow well region, a deep well region located between the shallow well region and the drift region, and a junction field effect region: in contact with the shallow well region, the drift region, and the deep well region; and having a junction field effect doping concentration of the first conductivity type. The FETs can include a hybrid channel formed by a portion of the junction field effect region, as influenced by the deep well region, and the shallow well region.

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Hillsboro, OR, United States of America

Scott Joseph Alberhasky