Agere Systems Inc.

Agere Systems Guardian Corp.

Scott Jessen

John Martin McIntosh

Kurt George Steiner

Catherine B Vartuli

Erik Cho Houge

Susan Clay Vitkavage

Fred Anthony Stevie

Simon John Molloy

Brittin C Kane

Nace Layadi

Gerald Warren Gibson, Jr

Thomas Evans Adams

Steven Alan Lytle

Subramanian Karthikeyan

Gerald W Gibson, Jr

James W Blatchford, Jr

Isaiah O Oladeji

Joseph Ashley Taylor

Robert Y S Huang

Joshua Jia Li

Thomas S Frederick

Scott M Nagel

Steve Lytle

A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.

Mask layer and dual damascene interconnect structure in a semiconductor device

A semiconductor manufacturing method analyzes topography variations in three dimensions for each photolithographic level and determines critical dimension (CD) bias compensation as inputs to mask layout creation. Accurate predictions of topography variation for a specific mask design are made at the die level using known pattern density and CMP planarization length characteristics for a specific pattern. Exhaustive characterization of the photoresist response to de-focus and mask bias is determined by artificially expanding loss of CD through focus. Mask compensation to an expanded range of focus over all lines and spaces is maintained within the specification. 3D mask density data is obtained to determine the height component at each pixel location in the die. The resulting 3D OPC model is then utilized for mask creation.

Substrate topography compensation at mask design: 3D OPC topography anchored

A split barrier layer enables copper interconnect wires to be used in conjunction with low-k dielectric films by preventing the diffusion of N&#x2014;H base groups into photoresists where they can render the photoresist insoluble. The split barrier layer is disposed between the copper and the low-k dielectric and includes a nitrogen-containing, oxygen-free film which contacts the copper, and an oxygen-containing, nitrogen-free film which contacts the low-k dielectric film. The nitrogen-containing film prevents the formation of undesirable copper oxides, and the oxygen-containing film prevents the diffusion of N&#x2014;H base groups into the low-k dielectric films. The oxygen-containing film may be an oxygen-doped silicon carbide film in an exemplary embodiment. In another embodiment, a film stack of low-k dielectric films includes an etch-stop layer and hardmask each formed of oxygen-doped silicon carbide. The hardmask and etch-stop layer enable the formation of a dual-damascene opening in the film stack, and the film structure of the present invention precludes N&#x2014;H base groups from diffusing from the low-k dielectric films and neutralizing acid catalysts in the photoresist used to define the dual damascene opening.

Split barrier layer including nitrogen-containing portion and oxygen-containing portion

A film structure includes low-k dielectric films and N&mdash;H base source films such as barrier layer films, etch-stop films and hardmask films. Interposed between the low-k dielectric film and adjacent N&mdash;H base film is a TEOS oxide film which suppresses the diffusion of amines or other N&mdash;H bases from the N&mdash;H base source film to the low-k dielectric film. The film structure may be patterned using DUV lithography and a chemically amplified photoresist since there are no base groups present in the low-k dielectric films to neutralize the acid catalysts in the chemically amplified photoresist.

Structure and method for isolating porous low-k dielectric films

A semiconductor manufacturing automation method for analyzing a patterned feature formed on a semiconductor layer is disclosed. At least one patterned feature is scanned to generate an amplitude modulated waveform signal of the line and neighboring space characteristics. Signal processing is automatically performed on this waveform by an in-line computational source to extract known patterned features based on the profile of the amplitude modulated waveform signal. The extracted waveform segments are subjected to known geometric shapes to determine if the waveform indicates a normal or abnormal patterned feature on a semiconductor layer.

Abnormal photoresist line/space profile detection through signal processing of metrology waveform

The present invention provides a method of forming a dynamic template with a focused beam. The method includes forming a desired template that represents a desired image, forming an actual template that represents an actual image, such as a photolithographic mask or a semiconductor device feature, and comparing the desired template to the actual template to yield a deviation template. In one embodiment the deviation template is formed by subtracting the actual template from the desired template.

Method of focused ion beam pattern transfer using a smart dynamic template

A method for analyzing a semiconductor surface having patterned features on the surface is disclosed. At least one patterned feature is scanned to produce a scanned waveform signal having signal segments corresponding to characteristic surface portions of the patterned feature. The signal segments are processed using an auto-correlation function to produce an auto-correlation signal for each characteristic surface portion of the patterned feature. A reference signal having signal segments corresponding to characteristic surface portions of a known patterned feature is provided and each segment of the auto-correlation signal is compared to the respective signal segments of the reference signal.

Method analyzing a semiconductor surface using line width metrology with auto-correlation operation

A patterned transfer process in the manufacture of a semiconductor device is monitored. Patterned features formed on a semiconductor layer to be etched are scanned for generating a first amplitude modulated waveform intensity signal. The first amplitude modulated waveform intensity signal is sampled to extract a first measurement population of critical dimension measurements. The patterned features are etched and then scanned for generating a second amplitude modulated waveform intensity signal. The second amplitude modulated waveform intensity signal is then sampled to extract a second measurement population of critical dimension measurements, which are then cross-correlated to obtain correlation values of the etching process.

Method of monitoring a patterned transfer process using line width metrology

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Orlando, FL, United States of America

Scott Jessen