International Business Machines Corporation

Intrenational Business Machines Corporation

Scott Jeffrey Schaffer

Melanie Jean Sandberg

Paul Merrill Greco

Glen Alan Jaquette

Paul Merril Greco

Mark Alfred Lantz

Roy Daron Cideciyan

Simeon Furrer

Robert Allan Hutchins

Keisuke Tanaka

Ernest Stewart Gale

Robert Allen Hutchins

Steven Ross Bentley

Hisato Matsuo

Sushama M Paranjape

Stephen C West

Rika Nagahara

Charles E Bailey

Carl A Hassell

In one embodiment, a method includes reading a codeword stored to a memory, computing a syndrome word based on a product of the codeword and a parity check matrix derived from a linear block code, setting a flag to a first value indicating that the codeword includes no errors in response to a first determination requiring that the syndrome word is an all-zero vector, setting the flag to a second value indicating that the codeword includes exactly one single-bit error in response to a second determination requiring that the syndrome word equals a column of the parity check matrix, setting the flag to a third value indicating that the codeword includes an odd number of multiple bit errors in response to a third determination, and setting the flag to a fourth value indicating that the codeword includes an even number of multiple bit errors in response to a fourth determination.

Detection of multiple bit errors in random access memories

Provided is a data storage drive for encrypting data, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a session key, wherein a result is a data key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium. Also provided is a system, comprising a microprocessor and circuitry coupled to the microprocessor and adapted to receive a session encrypted data key and to decrypt the session encrypted data key using a private key, wherein a result is a secret key that is capable of being used to encrypt clear text and to decrypt cipher text written to a storage medium.

Key encryption and decryption

In one embodiment, a method includes loading first data into a first buffer of an interposer during a first time period and loading second data into a second buffer of the interposer and performing a first decoding operation on the first data using a first decoder during a second time period. The method includes loading third data into a third buffer of the interposer, performing the first decoding operation on the second data using the first decoder, and performing a second decoding operation on the first data using a second decoder during a third time period. Moreover, the method includes loading fourth data into a fourth buffer of the interposer, performing the first decoding operation on the third data using the first decoder, and performing the second decoding operation on the second data during a fourth time period. The first and second decoding operations are C1 or C2 decoding operations.

Pipelined architecture for iterative decoding of product codes

A method for equalizing the bandwidth of requesters using a shared memory system is disclosed. In one embodiment, such a method includes receiving multiple access requests to access a shared memory system. Each access request originates from a different requester coupled to the shared memory system. The method then determines which of the access requests has been waiting the longest to access the shared memory system. The access requests are then ordered so that the access request that has been waiting the longest is transmitted to the shared memory system after the other access requests. The requester associated with the longest-waiting access request may then transmit additional access requests to the shared memory system immediately after the longest-waiting access request has been transmitted. A corresponding apparatus and computer program product are also disclosed.

Equalizing bandwidth for multiple requesters using a shared memory system

A method and system for generating ciphertext and message authentication codes utilizing shared hardware are disclosed. According to one embodiment, a method is provided of generating ciphertext message data and message authentication codes utilizing shared authenticated encryption unit hardware. In the described embodiment, plaintext message data is received at an authenticated encryption unit which comprises first and second authenticated encryption hardware modules. Thereafter, a first message authentication code (MAC) associated with a first authenticated encryption mode and a second MAC associated with a second authenticated encryption mode are generated. More specifically, the first MAC is generated utilizing the plaintext message data and first authenticated encryption hardware module and ciphertext message data and the second MAC are generated utilizing the plaintext message data and second authenticated encryption hardware module.

Method and system for generating ciphertext and message authentication codes utilizing shared hardware

A method, system, and apparatus for dynamically validating a data encryption operation are disclosed. In one embodiment, a method is provided which comprises decrypting a first sequential data element of a plurality of data elements substantially in parallel with the encryption of a second sequential data element of the plurality, where the first element comprises first data and first encryption validation metadata. In response to the decryption, second encryption validation metadata is generated utilizing the first data. Thereafter, a determination is made whether the first element has been validly encrypted based upon a comparison of the first and second metadata. In other embodiments, an encryption validation indicator may be generated (e.g., to notify a user of a detected encryption error and/or to mark a portion of data for re-encryption), further encryption operations may be suspended, and/or the storage of the first data element may be controlled following such a determination.

Method, system, and apparatus for dynamically validating a data encryption operation

Provided are a method, system, and article of manufacture that maintains, at a decryption unit, and expected key identifier and an expected initialization vector. A key identifier and an initialization vector are received at the decryption unit, wherein a plurality of encrypted data records are preceded by the key identifier and the initialization vector in a data stream, and wherein the plurality of encrypted data records have been encrypted with a cryptographic key that is recoverable by the decryption unit from the key identifier. An initiation is made of the reading of the plurality of encrypted data records of the data stream, in response to determining at the decryption unit that the received key identifier matches the expected key identifier. Certain embodiments are implemented in a storage library, comprising at least one storage drive, and at least one decryption unit included in the at least one storage drive, wherein in certain embodiments the storage library is a tape library. Certain additional embodiments are implemented in a storage drive, comprising a removable storage medium and at least one decryption unit coupled to the removable storage medium, wherein in certain embodiments the storage drive is a tape drive.

Detection and handling of encryption key and initialization vector

Provided are a method, system, and article of manufacture, wherein a first write only register is maintained in an encryption engine of a cryptographic unit. A second write only register is maintained in a decryption engine of the cryptographic unit. A cryptographic key is written in the first write only register and the second write only register, wherein the cryptographic key is inaccessible for reading from any entity that is external to the cryptographic unit.

Maintaining encryption key integrity

Provided are a method, system and article of manufacture, wherein a cryptographic key generator generates a cryptographic key. The cryptographic key generator encrypts the cryptographic key with a session key that is available to both the cryptographic key generator and a cryptographic unit. The encrypted cryptographic key is transmitted across a link from the cryptographic key generator to the cryptographic unit.

Secure transmission of cryptographic key

A method and apparatus for testing digital read channel circuits within a data storage device includes a digital read channel circuit coupled to a simulated impulse response module are disclosed. The data storage device includes a digital read channel circuit coupled to a simulated impulse response module. A pseudo analog-to-digital waveform is generated by the simulated impulse response module is input into the digital read channel circuit. The digital read channel circuit then decodes the pseudo analog-to-digital waveform to form a set of binary data. After receiving the set of binary data, a formatter/deformatter verifies the correctness of the binary data, such that the integrity of the digital read channel circuit and the formatter/deformatter can be determined.

Method and apparatus for testing the digital read channel circuit of a data storage device

A data storage system has error detecting and correcting system having three error codes. The data are arranged logically as a three-dimensional array consisting of a plurality of logically rectangular blocks of data. Each block of data has columns and rows of data. A first error code that corrects errors creates a first redundancy in each of the columns. A like-positioned block row of data in each of the blocks constitutes an array row of data. The array rows are grouped into sets of array rows, the number of array rows in each set vary inversely with a number of tracks of a record medium that concurrently receive the data for recording. Each set of data are recorded serially by bit in respective tracks of the tape record medium. Before recording, the block rows are logically rotated (end-around shifted) within each of the array rows. The block row shifting is different for each set such that the lateral alignment of data are changed for avoiding medium defects extending transversely of the tracks from creating excessive errors in any column of data. After the block row shifting, a second error code is applied to each block row while a third error code is applied to each array row. Readback is a reversal of the writing process. Error pointers are generated from the second and third redundancies as well as from signal and data format errors.

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Tucson, AZ, United States of America

Scott Jeffrey Schaffer