Graf Research Corporation

Scott Jeffery Harper

Jonathan Peter Graf

Ali Asgar Ali Akbar Sohanghpurwala

Carlton Fraley

Alan Cook

Ali Asgar Sohanghpurwala

Timothy Dunham

A computer system traces an original electronic design automation (EDA) implementation process for electronic hardware designs. The original EDA implementation process includes multiple subprocesses to convert a hardware model to a physically-realized electronic circuit. The system inputs a cryptographic key and design information that includes the hardware model, constraints, properties, implementation settings, and other directives for directing the conversion. The cryptographic key and design information are processed to generate a sequence of instructions to execute and provide traceability of each subprocess. For each subprocess, the system gathers intermediate design state and implementation settings resulting from or influencing execution of the subprocess; combines the intermediate design state and implementation settings into a data string and determines a cryptographic hash value for the data string; digitally signs the cryptographic hash value using a digital signature certificate derived from the cryptographic key to generate a signed hash; stores the signed hash and identifiers associated with data files used for determining the cryptographic hash value to an electronic ledger to generate an updated electronic ledger; authenticates the signed hash from the electronic ledger to generate an authenticated signed hash; reconstructs a hash from the data files stored in the electronic ledger to generate a reconstructed hash; compares the authenticated signed hash with the reconstructed hash, and in response to a mismatch, generates an error signal. The steps are repeated for each subsequent subprocess, and the traced EDA implementation process results are stored in memory.

Computer technology to ensure an electronic design automation (EDA) implementation for electronic circuitry is traceable, auditable, and reproducible

An apparatus, method, and system assess the trustworthiness of a design representation while maintaining its confidentiality and thwarting attempts at unauthorized access, misappropriation, and reverse engineering of confidential proprietary aspects of the design representation and/or its bit stream. A utility/tool is provided for trust assessment and verification of designs and/or bit streams. The utility/tool may be instantiated on a semiconductor device or implemented as a utility executable on a mobile computing device or other information processing system, apparatus, or network.

Verification of bitstreams

An apparatus, method and system are disclosed which may be used for assessing the trustworthiness of a particular proprietary microelectronics device design representation in a manner that will maintain its confidentiality and, among other things, thwart attempts at unauthorized access, misappropriation and reverse engineering of the confidential proprietary aspects contained in the design representation and/or its bit stream design implementation format. The disclosed method includes performing a process for assessing/verifying a particular microelectronics device design representation and then providing some indication of the trustworthiness of that representation. An example utility/tool which implements the disclosed method is described that is particularly useful for trust assessment and verification of FPGA designs. The described utility/tool may be instantiated on a semiconductor device or implemented as a software utility executable on a mobile computing device or other information processing system, apparatus or network.

Growing community of inventors

Blacksburg, VA, United States of America

Scott Jeffery Harper