Infineon Technologies Ag

International Business Machines Corporation

Samsung Electronics Co., Ltd.

Scott Jansen

Alois Gutmann

Roland Hampp

Randy William Mann

Oliver Desmond Patterson

Min Chul Sun

Stress-inducing structures, methods, and materials are disclosed. In one embodiment, an isolation region includes an insulating material in a lower portion of a trench formed in a workpiece and a stress-inducing material disposed in a top portion of the trench over the insulating material.

Stress-inducing structures, methods, and materials

Semiconductor integrated test structures are designed for electron beam inspection of semiconductor wafers. The test structures include pattern features that are formed in designated test regions of the wafer concurrently with pattern features of integrated circuits formed on the wafer. The test structures include conductive structures that are designed to enable differential charging between defective and non-defective features (or defective and non-defection portions of a given feature) to facilitate voltage contrast defect detection of CMOS devices, for example, using a single, low energy electron beam scan, notwithstanding the existence of p/n junctions in the wafer substrate or other elements/features.

Semiconductor integrated test structures for electron beam inspection of semiconductor wafers

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Boulder, CO, United States of America

Scott Jansen