Mitsubishi Electric and Electronics U.s.a., Inc.

International Business Machines Corporation

Cadence Design Systems, Inc.

Mitsubishi Semiconductor America, Inc.

Renesas Technology America, Inc.

Scott J Tucker

James C Morizio

Geoffrey B Stephens

Tobing Soebroto

Dan Robbins

Michael C Hoke

James DeMaris

Wei Hong

Jose L Medero

Elizabeth Danford

A circuit for that includes isolation logic is disclosed. In one aspect, circuit comprises at least one input/output (I/O) cell, the I/O cell further including circuitry functions, isolation control logic, and a capability to receive power to the I/O cell from a power domain source. In a second aspect an integrated circuit comprises a physical layer (PHY) logic and at least one input/output (I/O) cell in communication with the PHY logic. The I/O cell capable of receiving power from a plurality of power domains. The I/O cell includes an isolation control logic and an I/O logic capable of receiving power from one power domain of a plurality of power domains, wherein the I/O logic and the isolation controller are arranged in communication through a level shifter for shifting power to maintain an active operation of the at least one I/O cell; wherein since the isolation control logic is within the I/O cell, only one active power domain of the plurality of power domains is required.

Power shutdown with isolation logic in I/O power domain

Methods and apparatus to detect terminal open circuits and short circuits to ground in inductive head write drivers are presented. A exemplary method is provided for detecting a short-circuit condition at at least one of a pair of write head terminals of a write driver, the write driver producing a write current that, when passed through a inductive head assembly coupled to the pair of write head terminals, polarizes the inductive head according to a direction of the write current. The method includes the step of generating a first current that is proportional to at least a portion of the write current that flows in a first direction into a first write head terminal of the write driver. A second current is generated that is proportional to at least a portion of the write current that flows in a second direction, opposite the first direction, into a second write head terminal of the write driver. A short-circuit condition at at least one of the first and second write head terminals is detected when an average value of the first current is different from an average value of the second current by a predetermined amount.

Methods and apparatus for detecting terminal open circuits and short circuits to ground in inductive head write driver circuits

Shorts are detected in terminals fed current by a driver connected to the terminals. To detect terminal-to-ground shorts, at least one virtual driver is connected to the driver for processing an output of the driver, and a detector detects if a short has occurred, based on an output of the virtual driver, by detecting when an output of the virtual driver exceeds a first threshold. If the detector detects that the output of the virtual driver has exceeded the first threshold, this indicates a terminal-to-ground short. To detect terminal-to-terminals shorts, a detector detects when an output of the driver drops below a second threshold. If the detector detects that the output of the driver has dropped below the second threshold, this indicates a terminal-to-terminal short. Shorts may be detected in terminals in one or more write heads. The driver, virtual driver, and detector may be included in a preamplifier. Detecting shorts in this manner avoids the loss of data without impeding performance of the write driver.

System and method for terminal short detection

An arrangement for reading data from a magnetic data carrier using a magneto-resistive (MR) head. A bias current source supplies the MR head with a bias current adjustable after MR head change. A bias current control signal having multiple control bits is used for adjusting the bias current. A noise shunting capacitor is connected to the MR head for reducing noise caused by the bias current. A discharging circuit is coupled to the noise shunting capacitor to discharge the capacitor when the bias current is being adjusted, in order to reduce bias current settling time. The discharging circuit comprises a pair of switches for each control bit of the bias current control signal. One of the switches is connected to a positive plate of the noise shunting capacitor, and another switch is coupled to a negative plate of the capacitor. The switches are controlled by a one-shot multivibrator triggered by a falling edge of the corresponding control bit. Weighting resistors are connected to each switch for weighting a discharge current produced by the switch in accordance with a position of the corresponding control bit so as to produce a larger discharge current in response to a higher-order control bit of the bias current control signal.

Reducing bias current settling time in magneto-resistive head pre-amplifiers

A sigma-delta analog-to-digital (A/D) converter has an analog modulator, and an adjustable reference voltage circuit that provides a reference voltage to the analog modulator along a feedback path during A/D conversion. The reference voltage circuit includes a reference voltage generator that provides a plurality of positive and negative polarity signals to a gain multiplexer. The gain multiplexer selectively supplies a pair of positive and negative polarity signals to the analog modulator based on a select signal produced by a gain register and a microprocessor interface bus that together allow adjustment of the range of operation and performance of the sigma-delta A/D converter. This adjustment is made based on a particular application in which the converter is implemented; as the relative input power of an input signal changes, the sigma-delta A/D converter as dynamically adjusted, realizes higher performance.

Programmable dynamic range sigma delta A/D converter

A circuit and method for compensating for the output phase delay of an external clock signal utilizes a phase-locked loop that includes an output port of an integrated circuit device. In the phase-locked loop, a phase detecting circuit compares the external clock signal with an output signal from the output port, producing a phase error signal. The phase error signal is applied to a skew compensator to generate an internal clock signal. The internal clock signal is fed back through the output port to the phase detecting circuit. Clock jitter is reduced by reducing the gain of the skew compensator after a phase lock condition occurs in the compensation circuit.

Adaptable output phase delay compensation circuit and method thereof

A tristate buffer circuit for mixed voltage applications. The circuit is built from field effect transistors and is used as an output buffer in applications where a low voltage component needs to drive both components which are powered by the same low voltage and components which are powered by a higher voltage. The circuit uses a floating n-well technique in combination with a pass-gate network, a one-shot circuit, and a process-dependent bias voltage reference. It is particularly useful on CMOS semiconductor chips which have bus interfaces, such as local area network (LAN) protocol chips.

Growing community of inventors

Raleigh, NC, United States of America

Scott J Tucker