Hewlett-packard Development Company, L.p.

Hewlett Packard Enterprise Development LP

Other

Scott J Norton

Hyun Duk Kim

Thomas L Vaden

Swapneel Kekre

James R Callister

A system for providing features at launch to an application. The system may execute a user-space launcher application. To execute the launcher application, the computing system may: wrap a process creation function with a process creation wrapper function, preload a function library comprising the process creation function, launch an application specified to the launcher application, intercept a call to the process creation function of the launched application with the process creation wrapper function, create a process on behalf of the launched application using the process creation function, and provide a feature at launch to the process of the launched application based on a parameter specified to the launcher.

Process and thread launch features

A sanding glove including: a glove body fabricated from a base layer of material, wherein the glove body includes a hand opening, a backing, a palm, a thumb compartment, an index finger compartment, a middle finger compartment, a ring finger compartment and a small finger compartment, wherein each of the finger compartments include palm sides, back sides and fingertip ends; a first strip of hook fastener material attached to the palm side of the thumb compartment; second, third, fourth, and fifth strips of hook fastener materials attached to the palm side of the index finger, the middle finger, the ring finger, and the small finger compartments; and wherein a loop backed sanding pad of any desired shape can be attached to at least one of the strips of hook fastener material to facilitate sanding.

Sanding glove and associated sanding assembly

An operating system provides instructions for execution by plural hardware threads of a multithreaded core of a processor, the plural hardware threads appearing as separate logical processors to the operating system. An abstraction layer converts respective identifiers of the plural hardware threads to a core identifier representing the core. The abstraction layer presents the core identifier to a user application to hide the plural hardware threads from the user application, and to present the core as a single-threaded core to the user application.

Abstracting a multithreaded processor core to a single threaded processor core

In an embodiment of the invention, an apparatus and method to abstract a multithreaded processor core to single threaded processor core include performing the steps of: viewing, by an operating system, a first hardware thread and a second hardware thread in a processor core; and viewing, by a user application, the first hardware thread and the second hardware thread as a single CPU object.

An embodiment of the invention provides an apparatus and method for accurate measurement of utilizations in a hardware multithreaded processor core. The apparatus and method perform the acts including: determining idle time spent cycles which are cycles that are spent in idle by a hardware thread in a processor core; determining idle consumed cycles which are cycles that are consumed in the idle time spent cycles, by the hardware thread; and determining at least one of a processor core utilization and a logical processor utilization based upon at least one of the idle time spent cycles (d) and idle consumed cycles (d).

Accurate measurement of multithreaded processor core utilization and logical processor utilization

A determination of processor core utilization by a plurality of hardware threads over a time interval is made through a division of a length of the time interval by a total count of the plurality of hardware threads.

Hardware threads processor core utilization

An arrangement, in a computer system, for coordinating scheduling of threads on a plurality of processor sets (PSETs). The arrangement includes a first processor set (PSET) having a first set of scheduling resources, the first set of scheduling resources. The arrangement further includes a second processor set (PSET) having a second set of scheduling resources. The first set of scheduling resources is configured to schedule threads assigned to the first PSET only among processors of the first PSET, and the second set of scheduling resources is configured to schedule threads assigned to the second PSET only among processors of the second PSET.

Per processor set scheduling

A method in a computer system for coordinating scheduling of threads among a plurality of processors. The method includes collecting, using a cooperative scheduling component (CSC), system data pertaining to the plurality of processors. The method further includes calculating, using the CSC, unified scheduling-related parameters (USRPs) from the system data. The method additionally includes furnishing the USRPs from the CSC to at least two of a thread launcher, a thread balancer, and a thread stealer, whereby at least two of the thread launcher, the thread balancer, and the thread stealer employ the USRPs to perform their respective scheduling-related tasks.

Adaptive cooperative scheduling

In an embodiment of the invention, a method for dynamic hardware multithreading, includes: using a hardware halt function or a hardware yield function in a processor core in order to enable or disable a hardware thread that shares the core; wherein the hardware thread is disabled by placing the hardware thread in a halt state or yield state, and allowing another hardware thread to utilize the core.

Dynamic hardware multithreading and partitioned hardware multithreading

A computer-implemented method for traversing a first set of objects in a first dynamic list in a computer system. The method includes partitioning copies of the first set of objects into a plurality of second dynamic lists, each of the plurality of second dynamic lists being configured to contain a subset of the copies of the first set of objects, copies of the first set of objects being disposed in the plurality of second dynamic lists. The method also includes traversing the plurality of second dynamic lists using a plurality of traversal threads, thereby causing at least some of the copies of the first set of objects to be traversed in parallel.

Growing community of inventors

San Jose, CA, United States of America

Scott J Norton