Intel Corporation

University of Virginia Patent Foundation

The University of Texas System

Scott J Maddox

Anand S Murthy

Karthik Jambunathan

Joe C Campbell

Seth Bank

Tahir Ghani

Szuya S Liao

Cory C Bomberger

Joseph M Steigerwald

Jenny Hu

Pratik A Patel

Ritesh Jhaveri

Yaojia Chen

Orb Acton

Min Ren

Madison Woodson

Wenlu Sun

Techniques and mechanisms for providing functionality of a transistor which comprises a conformal layer of a gate work function silicide. In an embodiment, the transistor comprises a channel region and a gate dielectric which extends and adjoins the channel region. The gate dielectric also adjoins a layer structure of the transistor, the layer structure comprising a silicide. The silicide includes silicon and a component D which comprises a non-metal element from one of Groups IIIa, IVa, or Va. In another embodiment, the silicide further comprises a component M which includes a transition metal element from one of Groups IVb, Vb, VIb, VIIB, or VIIIb and/or which includes a metal element from one of Groups IIIa, IVa, or Va.

Silicide structure of an integrated transistor device and method of providing same

Techniques for forming contacts comprising at least one crystal on source and drain (S/D) regions of semiconductor devices are described. Crystalline S/D contacts can be formed so as to conform to some or all of the top and side surfaces of the S/D regions. Crystalline S/D contacts of the present disclosure are formed by selectively depositing precursor on an exposed portion of one or more S/D regions. The precursor are then reacted in situ on the exposed portion of the S/D region. This reaction forms the conductive, crystalline S/D contact that conforms to the surface of the S/D regions.

Forming crystalline source/drain contacts on semiconductor devices

Techniques are disclosed for forming transistors employing non-selective deposition of source and drain (S/D) material. Non-selectively depositing S/D material provides a multitude of benefits over only selectively depositing the S/D material, such as being able to attain relatively higher dopant activation, steeper dopant profiles, and better channel strain, for example. To achieve selectively retaining non-selectively deposited S/D material only in the S/D regions of a transistor (and not in other locations that would lead to electrically shorting the device, and thus, device failure), the techniques described herein use a combination of dielectric isolation structures, etchable hardmask material, and selective etching processes (based on differential etch rates between monocrystalline semiconductor material, amorphous semiconductor material, and the hardmask material) to selectively remove the non-selectively deposited S/D material and then selectively remove the hardmask material, thereby achieving selective retention of non-selectively deposited monocrystalline semiconductor material in the S/D regions.

Transistors employing non-selective deposition of source/drain material

An avalanche photodiode, and related method of manufacture and method of use thereof, that includes a first contact layer; a multiplication layer, wherein the multiplication layer includes AlInAsSb; a charge, wherein the charge layer includes AlInAsSb; an absorption, wherein the absorption layer includes AlInAsSb; a blocking layer; and a second contact layer.

AllnAsSb avalanche photodiode and related method thereof

A staircase avalanche photodiode with a staircase multiplication region composed of an AlInAsSb alloy. The photodiode includes a buffer layer adjacent to a substrate and an avalanche multiplication region adjacent to the buffer layer, where the avalanche multiplication region includes a graded AlInAsSb alloy grown lattice-matched or psuedomorphically strained on either InAs or GaSb. The photodiode further includes a photoabsorption layer adjacent to the avalanche multiplication region, where the photoabsorption layer is utilized for absorbing photons. By utilizing AlInAsSb in the multiplication region, the photodiode exhibits a direct bandgap over a wide range of compositions as well as exhibits large conduction band offsets much larger than the smallest achievable bandgap and small valance band offsets. Furthermore, the photodiode is able to detect extremely weak light with a high signal-to-noise ratio.

Staircase avalanche photodiode with a staircase multiplication region composed of an AIInAsSb alloy

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Hillsboro, OR, United States of America

Scott J Maddox