International Business Machines Corporation

Scott J Hadderman

Kraig R White

K Paul Muller

Katie L Pizzolato

David E Douse

Andrew H Vogel

Timothy R Marchini

Daniel John Kolor

William F Relyea

Malcolm Scott Ware

Brian Samuel Beaman

Wei T Huang

William J Rooney

Peter Bergersen Yocom

Guillermo Jesus Silva

Daniel J Kearney

Emmanuel Yashchin

Richard D Wheeler

A modular refrigeration unit (MRU) health monitor includes a log data input configured to receive log data from an MRU, the log data comprising a plurality of datapoints, each of the plurality of datapoints comprising a position of a control valve of the MRU and a corresponding time; and MRU health monitoring logic configured to determine a plurality of MRU parameters from log data received on the log data input; determine a plurality of MRU health flags based on the MRU parameters; add the plurality of MRU health flags to determine an MRU health score; determine whether the MRU health score is higher than a replacement threshold; and indicate replacement of the MRU in the event the MRU health score is higher than the replacement threshold.

Modular refrigeration unit health monitoring

A method for modular refrigeration unit (MRU) health monitoring includes receiving log data on a log data input from the MRU by a MRU health monitor, the log data comprising a plurality of datapoints, each of the plurality of datapoints comprising a position of a control valve of the MRU and a corresponding time; determining by the MRU health monitor a plurality of MRU parameters from the log data; determining a plurality of MRU health flags based on the MRU parameters; adding the plurality of MRU health flags to determine an MRU health score; determining whether the MRU health score is higher than a replacement threshold; and indicating replacement of the MRU in the event the MRU health score is higher than the replacement threshold.

A method to reduce large temperature over/undershoot in a computer system. Using workload data, the method proactively modifies controls of mechanical cooling system to anticipate power and take appropriate actions to maintain temperature. Workload control modifies workload and scheduling to reduce power transients and subsequent temperature deviations. In addition, workload control allows more even distribution of temp across chips, allowing for even wear and reduction of small/ripple/noise temp oscillations. A system and program product for carrying out the method are also provided.

Proactive cooling of chips using workload information and controls

A method for insertion of inserting printed circuit card into socket connectors which prevents sockets from getting contaminated or damaged during the insertion of a printed circuit card comprises the steps of: inserting a cam for moving a socket connector's contacts outwardly so that they will not make contact with a card's edge when it is inserted between the contacts of the sockets connector as it is inserted, and after the printed circuit card is inserted the printed circuit card moving the printed circuit card until it makes contact with a stop in the socket connector, and after the printed circuit card has contacted the stop in the socket connector, moving the cam to a closed position allowing the printed circuit card to be seated, and seating the printed circuit card by moving it to cause and allow for an amount of wipe to clean the connector's contacts without contaminating or damaging the socket connector's contacts during the insertion of said printed circuit card.

Method for insertion of inserting printed circuit card into socket connectors

An exemplary embodiment of the invention is an interconnection system including a primary connector having a first detection contact coupled to a first voltage, a second detection contact coupled to said first voltage and a reference contact coupled to a second voltage. The interconnection system includes a secondary connector having a first contact, a second contact and a secondary reference contact. The second contact and secondary reference contact are electrically connected. The first contact makes electrical connection with the first detection contact, the second contact makes electrical connection with the second detection contact and the secondary reference contact makes electrical connection with the reference contact. When the second detection contact makes electrical connection with the second contact, the second detection contact is connected to the second voltage.

Interconnection system

A current generation, quad RAS, single CAS, stacked component ( ) including four 4 Mb&times;4 bits 11/11 DRAMs ( ) is arranged to emulate a next generation 16 Mb&times;4 bits 12/12 DRAM. The (24) bit address signal provided by memory controller ( ) includes a row address of 12 bits and a column address of 12 bits. Each DRAM ( ) within the current generation DRAM component ( ) requires only 11 row address bits and 11 column address bits. The additional 1 row address bit and 1 column address bit are provided to decoder logic ( ). The additional row address bit is decoded by the decoding logic ( ) to direct the RAS signals over two of the four RAS lines ( ), thereby activating the two signaled DRAMs. The additional column address bit is then decoded by decoding logic ( ) to de-activate one of the two signaled DRAMs , leaving only one DRAM activated. CAS line ( ) directs the CAS signal to all of the stacked DRAMs ( ). The combination of both RAS and CAS is provided to only one of the plurality of current generation DRAMs, thereby permitting access to that particular current generation DRAM.

Emulation of next generation DRAM technology

An exemplary embodiment of the invention is a controller for use in an interconnection system having a primary connector and a variable number of secondary connectors. The primary connector includes a first detection contact and a second detection contact. The controller includes a first detection port connected to the first detection contact and a second detection port connected to the second detection contact. The controller also includes a processor for monitoring a first signal at the first detection port and a second signal at the second detection port and determining a number of secondary connectors in response to the first signal and the second signal.

Controller for use in an interconnection system

A method and apparatus for addressing multi-bank memory. The method includes generating a first bank select and generating a first row address. The first row address is stored and presented as a second bank select during an activate portion of the memory cycle. During an access portion of the memory cycle, a first bank select is generated and the saved second bank select is retrieved from storage. The first bank select and retrieved second bank select identify a bank of memory. The apparatus includes a storage device for saving the second bank select. The second bank select may be stored based on the value of the first bank select.

Method and apparatus for addressing multi-bank memory

A method and apparatus for detecting a supply voltage loss from a PCMCIA power source across a PCMCIA interface. The voltage loss may correspond for example, to the removal of a PCMCIA card from a PCMCIA host computer system. The invention provides for detection and reporting of said supply voltage loss to another apparatus capable of operating at lower voltage levels than that supplied by the PCMCIA power source. The rate of supply voltage loss is controlled, and an indication of the loss is provided to the other apparatus so as to allow sufficient time for the apparatus to take appropriate actions in response to the loss of supply voltage.

PCMCIA voltage loss detection

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generator coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

Apparatus for varying the refresh rate for a DRAM in response to

A method and apparatus for operating a DRAM while varying the supply voltage provided thereto. A memory system is designed to attach to a DRAM. The DRAM is capable of maintaining data stored therein until supply voltage is varied beyond a predetermined voltage change level without the performance of a refresh operation. The system includes a power source coupled to the DRAM for providing supply voltage thereto and a refresh signal generation device coupled to the DRAM for causing the DRAM to perform refresh operations wherein the charges associated with data bits stored within the DRAM memory cells are refreshed thereby maintaining the data integrity of data stored in the DRAM. The relative rates of supply voltage change and refresh signal provision are adjusted so as to ensure that refresh signals are provided to the DRAM prior to a point in time at which the change in supply voltage provided to the DRAM exceeds the predetermined voltage change level. Accordingly, it is possible to achieve reliable operation of the DRAM while the supply voltage provided thereto is varied.

Maintaining data integrity in DRAM while varying operating voltages

An apparatus may be used with a computer system having a PCMCIA interface. The apparatus employs a DRAM device and logic for converting the PCMCIA SRAM control signals into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The apparatus further provides controls for refreshing the DRAM device, and for arbitrating between the functions of refreshing the DRAM and providing for communication between the DRAM and the computer system. The apparatus further provides the power management functions required for operating a DRAM device in a PCMCIA environment.

PCMCIA SRAM card function using DRAM technology

A method for operating an apparatus including a DRAM with a computer system having a PCMCIA interface. The method includes the steps of converting the PCMCIA SRAM control signals sent by the computer system across the PCMCIA interface into DRAM control signals, so as to permit the communication of data and control signals between the computer system and the DRAM device. The method further includes refreshing the DRAM device and arbitrating between the refreshing of the DRAM and providing for communication between the DRAM and the computer system. The method further teaches providing power management functions required for operating a DRAM device in a PCMCIA environment.

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Pleasant Valley, NY, United States of America

Scott J Hadderman