Intel Corporation

Scott J Erlanger

James R Vash

Herbert H Hum

Eric J DeHaemer

Brinda Ganesh

Leena K Puthiyedath

Adrian C Moga

Ganesh Kumar

Richard Lawrence Carlson

David Bubien

Michelle M Sebot

Eric R Delano

Eric R DeLano

Danielle N Devereaux

Robert E Faber

A processor of an aspect includes a plurality of logical processors each having one or more corresponding lower level caches. A shared higher level cache is shared by the plurality of logical processors. The shared higher level cache includes a distributed cache slice for each of the logical processors. The processor includes logic to direct an access that misses in one or more lower level caches of a corresponding logical processor to a subset of the distributed cache slices in a virtual cluster that corresponds to the logical processor. Other processors, methods, and systems are also disclosed.

Processors having virtually clustered cores and cache slices

Methods and apparatus relating to retry based protocol with source/receiver FIFO (First-In, First-Out) buffer recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction are described. In an embodiment, upon detection of an error, a portion of transmitted data is stored in one or more storage devices before retransmission. Other embodiments are also described and claimed.

Retry based protocol with source/receiver FIFO recovery and anti-starvation mechanism to support dynamic pipeline lengthening for ECC error correction

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Boston, MA, United States of America

Scott J Erlanger