Xilinx, Inc.

Scott J Campbell

Thomas E Fischaber

Brian Philofsky

Walter A Manaker, Jr

Jaime D Lujan

Mario Escobar

Jeremy Blair Goolsby

Lyman D Lewis

Mona D Rideout

Paul J Glairon

A method and apparatus is provided for the automatic creation of timing constraints that are based upon input interface timing parameters entered through a graphical user interface that is associated with the one or more input interfaces. Ideal timing constraints are created from the input interface timing parameters for the one or more input interfaces, thereby enabling the analysis of the input interface(s) without requiring explicit constraints to be defined by the designer of the input interface(s). Timing constraints may, therefore, be automatically generated by the designer without the need for the designer to possess any detailed knowledge of the associated constraint language parameters. Once created, the automatically generated timing constraints are graphically displayed to the designer for verification and/or modification. The automated process removes any potential for improperly defining the input constraint language parameters associated with the input interface(s).

Apparatus and method for automated determination of timing constraints

A set of respective first delay values for paths from a clock source to nodes of the integrated circuit is generated. Respective second delay values for the paths are generated from the clock source through the clock tree to the nodes. Each first delay value corresponds to one of the second delay values for one of the nodes, and each is greater than the corresponding second delay value. A set of common delay values is generated, with each common delay value being a delay for a shared portion of the paths from the clock source through the clock tree to two of the nodes. The determined clock skew is based on the first delay value for a first node, the second delay value for a second node, and the common delay value for the shared portion of the paths from the clock source to the first and second nodes.

Determining clock skew between nodes of an integrated circuit

A digital logic circuit includes at least one stage. Each stage includes sum logic, combinatorial logic, and carry chain logic. The sum logic is configured to generate a first sum signal from a first set of three input signals. The combinatorial logic includes a carry generation portion and a sum generation portion. The carry generation portion is configured to generate a first carry signal from a second set of three input signals. The sum generation portion is configured to generate a second sum signal from the first sum signal and the first carry signal. The carry chain logic is configured to process the first sum signal, the second sum signal, and a carry-in signal to generate a carry-out signal and a third sum signal.

Digital logic circuit for adding three binary words and method of implementing same

A method of generating timing information for a circuit design can include determining static timing data for the circuit design and identifying a source of timing information for use in functional simulation of the circuit design. The method also can include updating the source of timing information to include at least a portion of the static timing data.

Timing annotation accuracy through the use of static timing analysis tools

A method of annotating timing information for a circuit design for performing timing analysis can include determining minimum and maximum clock path delays for registers of a circuit design and computing a difference between the maximum clock path delay and the minimum clock path delay for a destination register of the circuit design. The method further can include adjusting a register timing parameter for the destination register according to the difference and performing a timing verification on the destination register using the adjusted register timing parameter.

Annotating timing information for a circuit design for increased timing accuracy

Methods and circuitry are disclosed for decoding a keystream. A set of test bits is generated, and a set of attempted keystream bits are generated from differences between the test bits and an input set of cipher bits. A set of current keystream bits are generated from a current seed using a parallel feedback shift register, and the attempted keystream bits are compared to the current keystream bits. In response to attempted keystream bits being equal to the current keystream bits, the current keystream bits are fed back as a new current seed. In response to attempted keystream bits being not equal to the current keystream bits, the attempted keystream bits are fed back as the new current seed.

Parallel keystream decoder

A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOS. A blockRAM based zero-cycle latency read FIFO is also described.

Integrated circuit and method of reading data from a memory device

A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.

Integrated circuit and method of outputting data from a FIFO

A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOs. A blockRAM based zero-cycle latency read FIFO is also described.

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Frederick, CO, United States of America

Scott J Campbell