Qualcomm Incorporated

Scott Howard King

Bin Tian

Ahmad Jalali

Mark Leo Moeglein

Suhail Jalil

Alok Kumar Gupta

Simon Turner

Albert Scott Ludwin

Jian Lin

Yi Liang

William E Stein

Kerry Taylor

Methods, systems, and devices are described that provide for high precision synchronization between pairs of APs within a tracking area of a position location network. These tools and techniques may provide for incrementally synchronizing timers and oscillators located at respective APs. An AP may transmit a course frequency and timing acquisition signal that a second AP utilizes to estimate a frequency offset and/or time offset. The AP may transmit a subsequent fine frequency and timing acquisition signal which may be used to accurately adjust the estimated frequency offset and/or time offset of the second AP. The second AP may thus incrementally synchronize its oscillator(s) and/or timer(s). These techniques may be utilized over a multi-hop wireless network. The methods, systems, and devices may be applicable to single- and multi-floor location tracking systems.

High precision access point to access point synchronization in an indoor position location system

Techniques are provided which may be implemented in various methods, apparatuses, and/or articles of manufacture for use by a device that is operable in a plurality of modes, including 'higher power mode' and a 'lower power mode'. A timing circuit may be set based, at least in part, on a phase value obtained from a signal from a ground-based transmitter, and operation of the device may be selectively transitioned to a lower power mode wherein the device uses the timing circuit. In certain example implementations, operation of the device to the lower power mode may be selectively transition and based, at least in part, on a determination that one or more attribute values satisfy a profile test indicating that the electronic device is likely to be within a characterized environment, and/or a determination that the electronic device is likely to be in a constrained motion state.

Timing circuit calibration in devices with selectable power modes

Image processing techniques are described that reduce the amount of bandwidth required to read an image from memory for display. According to the techniques, a processor stores low change rate display layers in a memory such that a processor can read the display layers from the memory using a reduced amount of processing resources. An overlay module blends low change rate display layers into a combined overlay layer. A processor reads the overlay layer from the memory and selectively processes the overlay layer based on processing information for the overlay layer recorded in memory. The processor then blends the overlay layer and a high change rate video display layer to update a single image for display according to a high change rate. In addition, the overlay module updates the overlay layer based on the low change rate display layers according to a low change rate.

Blending multiple display layers

A display processor includes an interface unit, an instruction processor, a synchronization unit, at least one processing unit, and a device buffer. The interface unit receives input image data (e.g., from a main memory) and provides output image data for a frame buffer. The instruction processor receives instructions (e.g., in a script or list) and directs the operation of the processing unit(s). The synchronization unit determines the location of a read pointer for the frame buffer and controls the writing of output image data to the frame buffer to avoid causing visual artifacts on an LCD screen. The processing unit(s) may perform various post-processing functions such as region flip, region rotation, color conversion between two video formats (e.g., from YCrCb to RGB), up/down image size rescaling, alpha-blending, transparency, text overlay, and so on.

Display processor for a wireless device

Apparatus are provided, including an embedded display processor on a given chip. The apparatus may be an embedded device, for example, a mobile wireless communications device. More specifically, the apparatus may be a mobile phone, a portable gaming device, a video streaming device, or a GPS map drawing device. The display processor includes, on the same given chip, a rendering memory, from which pixels are rendered to a display device. The display processor further includes an image manipulation mechanism to manipulate pixels of a given image frame from source positions in a pre-manipulation buffer, to target positions in the rendering memory, the target positions corresponding to rendered positions in the given image frame. The display processor further includes a fetch mechanism to fetch, from the pre-manipulation buffer, a predetermined number of neighboring pixels including adjacent cross-row pixels traversing a plurality of rows while in their source positions, the adjacent cross-row pixels being intended for target positions in a common row in accordance with the manipulation to be performed by the manipulation mechanism. The display processor further includes a send mechanism to send, from the rendering memory, a set of the neighboring pixels, including adjacent common row pixels on a common row after having been manipulated, to the display device in accordance with a given dynamic refresh rate and scheme. The display processor further includes a reconfigure mechanism to periodically reconfigure a manner of assignment of addresses and physical locations for data stored in the rendering memory.

Virtual device buffer for embedded device

A method and system for transferring data bytes includes a first memory adapted to store a plurality of multiple-byte data words including header field bytes and one or more data field bytes. The system also includes a second memory adapted to store data field bytes transferred thereto from the first memory. A controller coupled to the first and second memories reads a data word including the header field byte and the one or more data field bytes out of the first memory. The system also includes a data packer coupled to the controller and the second memory. The controller and data packer cooperate to transfer the one or more data field bytes of the first data word read from the first memory to the second memory. The data packer stores only the one or more data field bytes in the second memory contiguously with a previously transferred and stored data field byte.

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Scott Howard King