Advanced Micro Devices Corporation

Exponential Technology, Inc.

Scott H McMahon

Stephen C Horne

James M Buchanan

A digital clock waveform generator and method for generating a clock signal are provided for a microprocessor or other digital circuit to provide on chip generation of internal clock signals having the same frequency as or a higher or lower frequency than an externally applied clock signal. In one embodiment, the waveform generator includes a delay chain and a control unit that matches the propagation delay of the delay chain to the period of an input timing signal. The waveform generator provides precise control of the duty cycles of the internally generated clock signals, and allows for rapid starting and stopping of the internal clock signals for power reduction functions. The waveform generator may further provide a system clock, and may include circuitry to precisely control the phase relationships between the various clock signals. The waveform generator is easily manufactured with digital circuitry that automatically compensates for changing environmental conditions such as operating voltage and temperature.

Digital clock waveform generator and method for generating a clock signal

An embedded ROM has a column of static RAM cells attached to the end of the row lines. When a row of ROM cells is activated by the row line, a RAM cell is also activated by the row line. The RAM cell indicates if the data in the selected row's ROM cells is valid. When the RAM cell indicates that the ROM data is not valid, external memory is read to obtain a patched instruction and the ROM data is ignored. The ROM's base address is translated to a base address in external memory of patch code. The ROM's offset address is used as the offset into the patch-code region of external memory. Thus address translation is minimal as the offset is not translated. A single ROM instruction can be updated by a single patch instruction in external memory, providing fine granularity of code updates. Longer update routines can be located in a patch-code overflow region of external memory. The updated instruction at the ROM's offset in the patch-code region can be a jump instruction to the longer update routine in the overflow region. Thus both single and multiple-instruction patches are possible.

Embedded ROM with RAM valid bits for fetching ROM-code updates from

A variable strength clock signal driver circuit and method of manufacturing the same are provided that accommodate either full or reduced drive strength of a generated clock signal. The clock driver circuit includes a package bonding option to select the desired strength of drive. Thus, the clock driver circuit may be operated at either fast or slow clock frequencies as determined by the system requirements. As a result, both high performance, high drive versions and low cost, low drive versions of a digital circuit such as a microprocessor may be provided that differ only in package bonding. The same set of masks may be used to produce either version of the circuit, thus permitting greater manufacturing flexibility and reducing cost. Furthermore, electromagnetic interference may be reduced by selecting the low drive strength option for cost sensitive applications.

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Austin, TX, United States of America

Scott H McMahon