Xilinx, Inc.

Scott H Jonas

Paul R Schumacher

Kumar Deepak

Jason Villarreal

Roger Ng

Anurag Dubey

Krishnan Subramanian

Ishita Ghosh

Event trace includes implementing a design for a data processing array of a target integrated circuit (IC) by, at least in part, adding a trace data offload architecture to the design. One or more selected tiles of the data processing array used by the design as implemented in the target IC are configured to generate trace data based on user-specified runtime settings for performing a trace. During execution of the design by the data processing array, trace data as generated by the one or more selected tiles of the data processing array is conveyed to a memory of the target IC using the trace data offload architecture. A trace report is generated from the trace data using a data processing system coupled to the target IC.

Data processing array event trace customization, offload, and analysis

Implementing a design for a heterogeneous computing platform can include storing, using a processor, profile data in a memory, wherein the profile data is generated from running the design for the heterogeneous computing platform and wherein the design includes a kernel adapted for hardware acceleration. Compliance of the design with a profile rule may be determined by comparing, using the processor, the profile data accessed from the memory with the profile rule. The profile rule can specify a design requirement for a hardware accelerated implementation of the kernel. Compliance of the design with the profile rule can be indicated, using the processor, based upon the comparing.

Implementation and evaluation of designs for heterogeneous computing platforms with hardware acceleration

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Niwot, CO, United States of America

Scott H Jonas